HD6473837FV Renesas Electronics America, HD6473837FV Datasheet - Page 290
HD6473837FV
Manufacturer Part Number
HD6473837FV
Description
IC H8/3837 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD6473837HV.pdf
(562 pages)
Specifications of HD6473837FV
Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
84
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Eeprom Size
-
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-BQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473837FV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473837FV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Figure 10.11 shows a typical flow chart for SCI3 initialization.
1
2
3
4
Select communication format in SMR
Set bits RIE, TIE, TEIE, and MPIE
in SCR3, and set TE or RE to 1
Clear TE and RE to 0 in SCR3
Set bits CKE1 and CKE0
interval elapsed?
Set BRR value
Figure 10.11 Typical Flow Chart when SCI3 Is Initialized
Has a 1-bit
Start
End
Yes
Wait
No
1.
2.
3.
4.
Select the clock in serial control register 3
(SCR3). Other bits must be cleared to 0.
If clock output is selected in asynchronous
mode, a clock signal will be output as soon
as CKE1 and CKE2 have been set.
During reception in synchronous mode, if
clock output is selected by bits CKE1 and
CKE0, a clock signal will be output as soon
as RE is set to 1.
Set the transmit/receive format in the serial
mode register (SMR).
Set the bit rate register (BRR) to the value
giving the desired bit rate.
This step is not required when an external
clock source is used.
Wait for at least a 1-bit interval, then set
bits RIE, TIE, TEIE, and MPIE, and set bit
TE or RE in SCR3 to 1. Setting TE or RE
enables SCI3 to use the TXD or RXD pin.
The initial states in asynchronous mode
are the mark transmit state and the idle
receive state (waiting for a start bit).
273
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