NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 399

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NUC130LE3CN

Manufacturer Part Number
NUC130LE3CN
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC130LE3CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NUC130LE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC130LE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
CAN Control Register (CAN_CON)
Register
CAN_CON
Bits
[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
Test
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Descriptions
Reserved
Test
CCE
DAR
Reserved
EIE
SIE
Offset
CAN0_BA+0x00
CCE
30
22
14
6
Reserved
There are reserved bits.
These bits are always read as ‘0’ and must always be written with ‘0’
Test Mode Enable
1 = Test Mode.
0 = Normal Operation.
Configuration Change Enable
1 = Write access to the Bit Timing Register (CAN_BTIME & CAN_BRP) allowed. (while Init
0 = No write access to the Bit Timing Register.
Disable Automatic Re-transmission
1 = Automatic Retransmission disabled.
0 = Automatic Retransmission of disturbed messages enabled.
Reserved
This is a reserved bit. This bit is always read as ‘0’ and must always be written with ‘0’.
Error Interrupt Enable
1 = Enabled - A change in the bits BOff or EWarn in the Status Register will generate an
0 = Disabled - No Error Status Interrupt will be generated.
Status Change Interrupt Enable
1 = Enabled - An interrupt will be generated when a message transfer is successfully
R/W
R/W
DAR
bit =1).
interrupt.
29
21
13
completed or a CAN bus error is detected.
5
Description
CAN Control Register
Reserved
28
20
12
4
- 399 -
Reserved
Reserved
Reserved
EIE
27
19
11
3
Publication Release Date: June 14, 2011
SIE
26
18
10
2
25
17
IE
9
1
Revision V2.01
Reset Value
0x0000_0000
Init
24
16
8
0

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