NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 391

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NuMicro™ NUC130/NUC140 Technical Reference Manual
5.13.6.10.6 Calculating Bit Timing Parameters
Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.
The resulting bit time (1/bit rate) must be an integer multiple of the APB clock period.
The bit time may consist of 4 to 25 time quanta, the length of the time quantum t q is defined by
the Baud Rate Prescaler with t q = (Baud Rate Prescaler)/f
. Several combinations may lead
apb_clk
to the desired bit time, allowing iterations of the following steps.
First part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times
measured in the APB clock. A maximum bus length as well as a maximum node delay has to be
defined for expandible CAN bus systems. The resulting time for Prop_Seg is converted into time
quanta (rounded up to the nearest integer multiple of t q ).
The Sync_Seg is 1 t q long (fixed), leaving (bit time – Prop_Seg – 1) t q for the two Phase Buffer
Segments. If the number of remaining t q is even, the Phase Buffer Segments have the same
length, Phase_Seg2 = Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1.
The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may not
be shorter than the IPT of the CAN controller, which, depending on the actual implementation,
is in the range of [0..2] t q .
The length of the Synchronization Jump Width is set to its maximum value, which is the
minimum of 4 and Phase_Seg1.
The oscillator tolerance range necessary for the resulting configuration is calculated by the
formulas given in Section 5.13.6.10.4: Oscillator Tolerance Range
If more than one configuration is possible, that configuration allowing the highest oscillator
tolerance range should be chosen.
CAN nodes with different system clocks require different configurations to come to the same bit
rate. The calculation of the propagation time in the CAN network, based on the nodes with the
longest delay times, is done once for the whole network.
The oscillator tolerance range of the CAN systems is limited by that node with the lowest
tolerance range .
The calculation may show that bus length or bit rate have to be decreased or that the stability of
the oscillator frequency has to be increased in order to find a protocol compliant configuration of
the CAN bit timing. The resulting configuration is written into the Bit Timing Register:
(Phase_Seg2-1) & (Phase_Seg1+Prop_Seg-1) & (SynchronisationJumpWidth-1)&(Prescaler-1)
Publication Release Date: June 14, 2011
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Revision V2.01