NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 385

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NuMicro™ NUC130/NUC140 Technical Reference Manual
Figure 5-84 Propagation Time Segment
In this example, both nodes A and B are transmitters, performing an arbitration for the CAN bus.
Node A has sent its Start of Frame bit less than one bit time earlier than node B, therefore node B
has synchronized itself to the received edge from recessive to dominant. Since node B has
received this edge delay (A_to_B) after it has been transmitted, B’s bit timing segments are
shifted with respect to A. Node B sends an identifier with higher priority and so it will win the
arbitration at a specific identifier bit when it transmits a dominant bit while node A transmits a
recessive bit. The dominant bit transmitted by node B will arrive at node A after the delay
(B_to_A).
Due to oscillator tolerances, the actual position of node A’s Sample Point can be anywhere inside
the nominal range of node A’s Phase Buffer Segments, so the bit transmitted by node B must
arrive at node A before the start of Phase_Seg1. This condition defines the length of Prop_Seg.
If the edge from recessive to dominant transmitted by node B arrives at node A after the start of
Phase_Seg1, it can happen that node A samples a recessive bit instead of a dominant bit,
resulting in a bit error and the destruction of the current frame by an error flag.
The error occurs only when two nodes arbitrate for the CAN bus that have oscillators of opposite
ends of the tolerance range and that are separated by a long bus line. This is an example of a
minor error in the bit timing configuration (Prop_Seg to short) that causes sporadic bus errors.
Some CAN implementations provide an optional 3 Sample Mode but the C_CAN does not. In this
mode, the CAN bus input signal passes a digital low-pass filter, using three samples and a
majority logic to determine the valid bit value. This results in an additional input delay of 1 tq,
requiring a longer Prop_Seg.
5.13.6.10.3 Phase Buffer Segments and Synchronization
The Phase Buffer Segments (Phase_Seg1 and Phase_Seg2) and the Synchronization Jump
Width (SJW) are used to compensate for the oscillator tolerance. The Phase Buffer Segments
may be lengthened or shortened by synchronization.
Publication Release Date: June 14, 2011
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Revision V2.01