LPC4310FET100,551 NXP Semiconductors, LPC4310FET100,551 Datasheet - Page 84
LPC4310FET100,551
Manufacturer Part Number
LPC4310FET100,551
Description
IC MCU 32BIT 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4310FET100,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
168K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4310FET100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.19.5.1 Features
7.20.1.1 Features
7.20.2.1 Features
7.20.1 Analog-to-Digital Converter (ADC0/1)
7.20.2 Digital-to-Analog Converter (DAC)
7.20 Analog peripherals
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Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
10-bit successive approximation analog to digital converter.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 to VDDA.
Sampling frequency up to 400 kSamples/s.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer
outputs 8 or 15, or the PWM output MCOA2.
Individual result registers for each A/D channel to reduce interrupt overhead.
DMA support.
10-bit resolution
Integral Non-Linearity (INL) <tbd>
Differential Non-Linearity (DNL) <tbd>
Monotonic by design (resistor string architecture)
Controllable conversion speed
Low power consumption
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 2.1 — 23 September 2011
4.
cy(WDCLK)
256 4) to (T
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
cy(WDCLK)
2
© NXP B.V. 2011. All rights reserved.
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