LPC4310FET100,551 NXP Semiconductors, LPC4310FET100,551 Datasheet - Page 72
LPC4310FET100,551
Manufacturer Part Number
LPC4310FET100,551
Description
IC MCU 32BIT 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC43xxr
Datasheet
1.LPC4310FET100551.pdf
(145 pages)
Specifications of LPC4310FET100,551
Core Processor
ARM® Cortex™-M4/M0
Core Size
32-Bit Dual-Core
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
168K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC4310FET100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
LPC4350_30_20_10
Objective data sheet
7.14.1.1 Features
7.14.1 AES decryption engine
7.14.2 One-Time Programmable (OTP) memory
7.15.1 Features
7.14 Security features
7.15 General Purpose I/O (GPIO)
The hardware AES engine can decode data using the AES algorithm.
The OTP provides 128 bit of memory for general purpose use and two 128-bit non-volatile
memories to store AES keys or other custom data.
The LPC4350/30/20/10 provide 8 GPIO ports with up to 31 GPIO pins each.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
All GPIO pins default to inputs with pull-up resistors enabled on reset.
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Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI)
and other external boot sources.
Secure storage of decryption keys.
Support for CMAC hash calculation to authenticate encrypted data.
Data is processed in little endian mode. This means that the first byte read from flash
is integrated into the AES codeword as least significant byte. The 16th byte read from
flash is the most significant byte of the first AES codeword.
AES engine performance of 1 byte/clock cycle.
Programmable through an on-chip API.
DMA transfers supported through the GPDMA.
Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
– Mask registers allow treating sets of port bits as a group, leaving other bits
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
be achieved.
unchanged.
All information provided in this document is subject to legal disclaimers.
Rev. 2.1 — 23 September 2011
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
© NXP B.V. 2011. All rights reserved.
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