MT90870AG Zarlink, MT90870AG Datasheet - Page 9

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Changes Summary
The following table captures the changes from the November 2005 issue.
The following table captures the changes from the December 2002 issue.
Page
Page
85
14
21
23
23
24
25
26
27
52
53
54
Package Drawing
Pin Description, C8i
Figure 6, Local Port Timing Diagram for
2,4,8 and 16 Mb/s stream rates
Figure 7, Backplane Port Timing Diagram
for 2, 4, 8, 16 and 32 Mb/s stream rates
Section 2.3. Backplane Frame Pulse Input
and Master Input Clock Timing
Figure 8, Backplane and Local Frame
Pulse Alignment for Data Rates of 2 Mb/s,
4 Mb/s, 8 Mb/s and 16 Mb/s
Figure 9, Backplane and Local Input
Channel Delay Timing Diagram (8 Mb/s)
Figure 10, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
16 Mb/s
Figure 11, Backplane and Local Input Bit
Delay Timing Diagram for Data Rate of
8 Mb/s
Section 13.1. Control Register (CR) Bit 6,
C8IPOL
Figure 18, Frame Boundary Conditions,
ST- BUS Operation
Figure 19, Frame Boundary Conditions,
GCI - BUS Operation
Item
Item
Zarlink Semiconductor Inc.
MT90870
9
Changed package Bill of Material with a thinner
substrate thickness.
The internal frame boundary alignment description
is changed from the clock rising or falling edge to
rising edge only. Also added description to specify
setting the C8IPOL bit in the Control Register to
one for clock rising edge alignment operation.
Changed C8i frame boundary active edge from
falling to rising edge.
Changed C8i frame boundary active edge from
falling to rising edge.
Removed the falling clock edge frame boundary
alignment option.
Changed C8i frame boundary active edge from
falling to rising edge.
Changed FPo and C8o to FPi and C8i respectively
and showing rising C8i frame boundary active
edge.
Changed FPo and C8o to FPi and C8i respectively
and showing rising C8i frame boundary active
edge.
Changed FPo and C8o to FPi and C8i
respectively.
Changed description to specify Bit 6, C8IPOL
must be set high for rising clock edge frame
boundary alignment operation.
Removed waveforms showing C8i falling edge
frame boundary option.
Removed waveforms showing C8i falling edge
frame boundary option.
Change
Change
Data Sheet