MT90870AG Zarlink, MT90870AG Datasheet
MT90870AG
Specifications of MT90870AG
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MT90870AG Summary of contents
Page 1
... Flexible 12 k Digital Switch (F12kDX) Ordering Information MT90870AG MT90870AG2 *Pb Free Tin/Silver/Copper *Note: the package thickness is different than the MT90870AG (see drawing at the end of the data sheet). • Local port accepts 16 ST-BUS streams with data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s, in any combination • ...
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... The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from the connection memory contents (Message Mode). MT90870 2 Zarlink Semiconductor Inc. Data Sheet ...
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... The microprocessor may monitor channel data in the Backplane and Local data memories. The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port. The MT90870 is manufactured body, 1.27 mm ball-pitch, 272-PBGA to JEDEC standard MS-034 BAL-2 Iss. A. MT90870 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1 Test Access Port (TAP 11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2.1 The Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.2.2.2 The Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 MT90870 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Local Output Bit Rate Resisters (LOBRR0-15 13.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.13.1 Backplane Input Bit Rate Registers (BIBRR0-31 13.13.2 Backplane Output Bit Rate Registers (BOBRR0-31 13.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.15 Revision Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MT90870 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 25 - GCI BUS Backplane Data Timing Diagram (32 Mb/s, 16 Mb/ Figure 26 - ST-BUS Local Timing Diagram (16 Mb/ Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/ Figure 28 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 29 - Output Driver Enable (ODE Figure 30 - Motorola Non-Multiplexed Bus Timing MT90870 List of Figures 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 42 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 43 - Local Output Bit Rate Register (LOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 44 - Output Bit Rate (LOBR) Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 45 - Backplane Input Bit Rate Register (BIBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 46 - Backplane Input Bit Rate (BIBR) Programming Table MT90870 List of Tables 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 49 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 50 - Revision Control Register (RCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MT90870 List of Tables 8 Zarlink Semiconductor Inc. Data Sheet ...
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... Changed description to specify Bit 6, C8IPOL must be set high for rising clock edge frame boundary alignment operation. Removed waveforms showing C8i falling edge frame boundary option. Removed waveforms showing C8i falling edge frame boundary option. 9 Zarlink Semiconductor Inc. Data Sheet Change Change ...
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... Changed C8i frame boundary active edge from falling to rising edge. Changed C8i frame boundary active edge from falling to rising edge. Changed FPo and C8o to FPi and C8i respectively and shows rising C8i frame boundary active edge. 10 Zarlink Semiconductor Inc. Data Sheet Change ...
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... A1 corner identified by metallized marking Figure 2 - MT90870 PBGA Connections (272 PBGA) Pin Diagram (as viewed through top of package) MT90870 11 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s (with 128 channels per stream), 4.096 Mb/s (with 64 channels per stream), or 2.048 Mb/s (with 32 channels per stream). The data-rate is independently programmable for each input stream Mb/s Mode, these pins are unused and should be externally connected to a defined logic level. 12 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s (with 32 channels per stream). The data-rate is independently programmable for each output stream. These pins are unused when the 32 Mb/s Mode is selected. Refer to descriptions of the BORS and ODE pins for control of the output High or High-Impedance state. 13 Zarlink Semiconductor Inc. Data Sheet ...
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... CS to enable the microprocessor port read and write operations. Read/Write (5 V Tolerant). This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Address Tolerant). These pins form the 15-bit address bus to the internal memories and registers. (Address A0 = LSB). 14 Zarlink Semiconductor Inc. Data Sheet ...
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... COPOL bit of the Control Register. C8o Output Clock (Three-state Output). A 8.192 MHz clock output. The clock falling edge or rising edge is aligned with the Local frame boundary, this is controlled by the COPOL bit of the Control Register. 15 Zarlink Semiconductor Inc. Data Sheet = 10mA). OL ...
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... When LOW, the BSTo0-31 and LSTo0- 31 outputs are driven high or high impedance (dependent on the BORS and LORS pin settings respectively) and the outputs BCSTo0-3 and LCSTo0-1 are driven low. When HIGH, the outputs BSTo0- 31, LSTo0-15, BCSTo0-3 and LCSTo0-1 are enabled. 16 Zarlink Semiconductor Inc. Data Sheet ...
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... LCSTo0-1 outputs driven low. Following initialization, the Local stream outputs may be set active or high impedance using the ODE pin per-channel basis with the LE bit of the Local Connection Memory. No Connect. No connection to be made. Internal Connects These inputs MUST be held LOW. 17 Zarlink Semiconductor Inc. Data Sheet ...
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... Local streams (LSTi0-15 and LSTo0-15) operated at 16.384 Mb/s. This allows data-rate conversion between 32.768 Mb/s and 16.384 Mb/s without loss to the switching capacity. MT90870 LSTo0-15 16 streams LSTi0-15 16 streams MT90870 BSTo0-31 32 streams LSTo0-15 16 streams MT90870 18 Zarlink Semiconductor Inc. Data Sheet LOCAL OUTPUT ...
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... Mb/s or lower data-rates on 32 input and 32 output streams. The Local streams (16 input and 16 output) may be operated at 16.384 Mb/s or lower data-rates. When the lower data-rates of 8.192, 4.096, and MT90870 MT90870 Total 24 input streams and 24 output streams 19 Zarlink Semiconductor Inc. Data Sheet LSTo0-15 BSTo24-31 LSTi0-15 BSTi24-31 ...
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... Mb/s - Non-32 Mb/s Mode 32.768 Mb Mb/s Mode 2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode Unused - 32 Mb/s Mode 2.048, 4.096, 8.192 or 16.384 Mb/s - Non-32 Mb/s Mode 32.768 Mb Mb/s Mode 20 Zarlink Semiconductor Inc. Data Sheet ...
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... Mb/s - Non-32 Mb/s Mode Unused - 32 Mb/s Mode 2.048, 4.096, 8.192 or 16.384 Mb/s 2.048, 4.096, 8.192 or 16.384 Mb/s Channel Channel Channel Channel Channel 0 6 Channel 0 1 Channel 0 7 Channel Zarlink Semiconductor Inc. Data Sheet Channel 255 Channel 255 Channel 127 Channel 127 Channel Channel ...
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... High-impedance state is controlled by the BE bit of the Backplane Connection Memory. The data source (i.e., from the Local or Backplane Data Memory) is determined by the BSRC bit of the Backplane Connection Memory. Refer to Section Connection Memory Bit Definition. MT90870 6.2, Backplane Connection Memory and Section 22 Zarlink Semiconductor Inc. Data Sheet 12.4, Backplane ...
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... Before the C8IPOL bit is set to one, the frame boundary will not be detected correctly. For the MT90870 Channel Channel Channel Channel Channel Channel Channel 0 6 Channel 0 1 Channel 0 7 Channel Zarlink Semiconductor Inc. Data Sheet Channel 510 Channel 511 Channel 510 Channel 511 Channel 255 Channel 255 Channel 127 Channel 127 ...
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... CH1 CH2 CH3 CH4 CH5 CH6 CH0 CH1 CH1 CH2 CH1 CH2 CH3 CH4 CH5 CH6 and 16 Mb/s 24 Zarlink Semiconductor Inc. Data Sheet CH2 CH3 CH4 CH5 CH7 CH8 CH9 CH10 CH11 CH2 CH3 CH4 CH5 CH7 CH8 CH9 CH10 CH11 ...
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... The Local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR15, corresponding to the Local data streams, LSTi0 to LSTi15, and the Backplane input delay is defined by the Backplane Input Delay registers, BIDR0 to BIDR31, which correspond to the Backplane data streams, BSTi0 to BSTi31. MT90870 Channel Delay, 2 Ch127 Ch0 Zarlink Semiconductor Inc. Data Sheet Ch126 Ch127 Ch125 Ch126 Ch125 ...
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... Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mb/s MT90870 Ch0 Bit Delay, 1/4 Ch0 Bit Delay, 1/2 Ch0 Bit Delay, 3/4 Ch0 Bit Delay, 1 Ch0 Ch255 Ch255 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 Ch1 Bit Delay, 7 1/2 Ch0 Bit Delay, 7 3/4 Ch0 ...
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... Mb/ Mb/s streams the advancement may cycles, -4 cycles or -6 cycles, which converts to MT90870 Ch0 Bit Delay, 1/4 Ch0 Bit Delay, 1/2 Ch0 Bit Delay, 3/4 Ch0 Bit Delay, 1 Ch0 Ch127 Ch127 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch1 Ch1 Ch1 Bit Delay, 7 1/2 Ch0 Bit Delay, 7 3/4 Ch0 ...
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... Table 2, LCSTo Allocation of Channel Control Bits to the Output Streams. MT90870 Ch255 Bit 0 Bit 7 Bit Advancement, -2 Ch255 Bit 0 Bit 7 Bit Advancement, -4 Bit 0 Bit 7 Bit Advancement, -6 Bit 0 Bit 7 Bit 6 28 Zarlink Semiconductor Inc. Data Sheet Ch0 Bit 6 Bit 5 Ch0 Bit 6 Bit 5 Ch0 Bit 4 Bit 6 Bit 5 Ch0 Bit 5 Bit 4 ...
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... Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams MT90870 Allocated Channel No. 16 Mb/s 8 Mb Zarlink Semiconductor Inc. Data Sheet ...
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... Allocated Channel No. 16 Mb/s 8 Mb etc etc etc etc etc etc Ch 254 Ch 127 254 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 255 Ch 127 Zarlink Semiconductor Inc. Data Sheet Frame Ch 0 Boundary etc etc ...
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... Note 2: The Channel Numbers presented relate to the data-rate selected for a specific stream. Note 3-1 to 3-4: See Section 4.1.1 for examples of Channel Control Bit for streams of different data-rates. MT90870 Allocated Channel No. 16 Mb/s 8 Mb etc etc etc 31 Zarlink Semiconductor Inc. Data Sheet Frame Ch 0 Boundary etc ...
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... Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE). MT90870 Channel 255 bits 7 Chan 0 Chan 0 Chan 127 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 One C16o period 32 Zarlink Semiconductor Inc. Data Sheet Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 Bit 0 Bit 7 Chan 0 Chan 63 Bit 0 Bit 7 Chan 0 ...
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... Table 3 - BCSTo Allocation of Channel Control Bits to the Output Streams MT90870 Channel No. BCSTo2 BCSTo3 16 Mb 3-2 3 (Non-32 Mb/s Mode) 33 Zarlink Semiconductor Inc. Data Sheet . 2 4 Mb ...
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... Ch 254 Ch 127 3 Ch 255 Ch 127 7 Ch 255 Ch 127 11 Ch 255 Ch 127 15 Ch 255 Ch 127 19 Ch 255 Ch 127 23 Ch 255 Ch 127 27 Ch 255 Ch 127 31 Ch 255 Ch 127 (Non-32 Mb/s Mode) (continued) 34 Zarlink Semiconductor Inc. Data Sheet 2 4 Mb Frame Boundary ...
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... Note 3-1 to 3-4: See Section 4.2.1 for examples of Channel Control Bit for streams of different data-rates. MT90870 Channel No. BCSTo2 BCSTo3 16 Mb etc etc etc etc (Non-32 Mb/s Mode) (continued) 35 Zarlink Semiconductor Inc. Data Sheet 2 4 Mb Frame Boundary etc etc ...
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... Backplane Connection Memory Bit Definition for setting the Backplane Output Enable Bit (BE). MT90870 Channel 255 bits 7 Chan 0 Chan 0 Chan 127 Chan 127 Bit 5 Bit 4 Bit 3 Chan 0 Bit 6 Chan 63 Bit 1 One C16o period 36 Zarlink Semiconductor Inc. Data Sheet Chan 127 Chan 127 Chan 0 Bit 2 Bit 1 Bit 0 Bit 7 Chan 0 Chan 63 Bit 0 Bit 7 Chan 0 ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams MT90870 Allocated Stream No. BCSTo1 BCSTo2 BCSTo3 511 511 511 511 3-2 3-2 3 (32 Mb/s Mode) 37 Zarlink Semiconductor Inc. Data Sheet 2 Channel No. 32 Mb/s ...
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... Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32 Mb/s Mode) (continued) Zarlink Semiconductor Inc. 2 Channel No Frame Boundary etc etc etc etc etc Ch 508 ...
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... Note 2: The Channel Numbers presented relate to the specific stream operating at a data-rate of 32.768 Mb/s. Note 3-1 to 3-4: See Section 4.2.2 for examples of Channel Control Bits. MT90870 Allocated Stream No. BCSTo1 BCSTo2 BCSTo3 511 511 511 etc etc etc etc (32 Mb/s Mode) (continued) 39 Zarlink Semiconductor Inc. Data Sheet 2 Channel No. 32 Mb/s Frame Boundary ...
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... Channel 1 Channel 510 bits 7-0 bits 7-0 Channel 1 Channel 510 bits 7-0 bits 7-0 One C16o cycle 40 Zarlink Semiconductor Inc. Data Sheet Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 Channel 511 bits 7-0 ...
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... Figure 16 - Constant Switch Delay: Examples of Different Stream Rates and Routing MT90870 Frames N+1 and N+2 Frame N 254 255 254 255 127 CH CH 127 CH CH 127 127 511 254 255 0 41 Zarlink Semiconductor Inc. Data Sheet Frame N 254 255 254 255 127 127 127 127 ...
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... Zarlink Semiconductor Inc. Data Sheet [7:0] [7:0] [7:0] [7:0] [8:0] ...
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... DS, R/W and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data memories, and the Local Connection and Data memories. Each Backplane memory has 8,192 locations and each Local memory has 4,096 MT90870 Zarlink Semiconductor Inc. Data Sheet ...
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... BORS, the output streams LSTo0-15 and BSTo0-31 are set to high or high impedance, and all internal registers and counters are reset to the default state. The RESET pin must remain low for two input clock cycles (C8i) to guarantee a synchronized reset release. MT90870 44 Zarlink Semiconductor Inc. Data Sheet ...
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... LSRC and LMM in the Local Connection Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The enable bits (LE and BE) of the respective connection memories should be set to HIGH to enable the outputs for the selected channels. MT90870 45 Zarlink Semiconductor Inc. Data Sheet ...
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... TCK pulse. This pin in internally pulled to V driven from an external source. MT90870 2 3 ...... ..... ..... ..... 254 2 3 ...... ..... ..... ..... 254 2 3 ...... ..... ..... ..... 254 Channels containing data (traffic) 46 Zarlink Semiconductor Inc. Data Sheet 255 255 2 255 _core when not DD_IO ...
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... Manufacturer ID, Bits <11:1>: 0001 0100 101 Header, Bit <0> (LSB): 1 11.3 Boundary Scan Description Language (BSDL) File A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149.1 test interface. MT90870 when not driven from an external source. . ...
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... The address bits of the microprocessor define the addresses of the streams and the channels. The LDM is configured as follows: Bit Name 15-8 Reserved Set to a default value of 0 7-0 LDM Local Data Memory Local Input Channel Data Table 10 - Local Data Memory (LDM) Bits MT90870 Description Description Description 48 Zarlink Semiconductor Inc. Data Sheet ...
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... Channel Address Bits. The binary value of these 9 bits represents the input channel number, when LMM is LOW. Bits LCAB7-0 transmitted as data when LMM is set HIGH. Table 12 - LCM Bits for Backplane(32 Mb/s Mode)-to-Local Switching MT90870 Description Description 49 Zarlink Semiconductor Inc. Data Sheet . ...
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... BORS pin. When the bit is high the channel is active. 12-9 BSAB3-0 Backplane Source Stream Address Bits. The binary value of these 4 bits represents the input stream number. BSAB3-0 are ignored when BMM is set HIGH in Message Mode. MT90870 Description (Non-32 Mb/s Mode) Description 50 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane Input Bit rate Register 0, BIBRR0 - Register 31, BIBRR31 012D 014C Backplane Output Bit rate Register 0, BOBRR0 - Register 31, BOBRR31 014D Memory BIST Register, MBISTR H 3FFF Revision control register, RCR H Table 15 - Address Map for Register (A14 = 0) MT90870 Description Register 51 Zarlink Semiconductor Inc. Data Sheet ...
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... LCSTo0-1 are driven low. When set HIGH, the BSTo0-31, LSTo0-15, BCSTo0-3 and LCSTo0-1 are enabled. MT90870 Description ODE Pin OSB bit BSTo0 - 31, LSTo0 - Output Control with ODE pin and OSB bit Table 16 - Control Register Bits 52 Zarlink Semiconductor Inc. Data Sheet Disable Disable Enable ...
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... Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 244 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i Figure 18 - Frame Boundary Conditions, ST- BUS Operation MT90870 Description Frame Boundary 53 Zarlink Semiconductor Inc. Data Sheet ...
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... When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except to abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the Control Register bit, MBP, to LOW. The BPR register is configured as follows. MT90870 Frame Boundary 54 Zarlink Semiconductor Inc. Data Sheet . ...
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... Clear Bit Error Rate Register for Backplane. A LOW to HIGH transition in this bit resets the Backplane internal bit error counter and the Backplane bit error (BBERR) register to zero. Table 18 - Bit Error Rate Test Control Register (BERCR) Bits MT90870 Description Description 55 Zarlink Semiconductor Inc. Data Sheet ...
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... When set HIGH, a PRBS sequence of length 2 port. When set LOW, a PRBS sequence of length 2 Local port. Table 18 - Bit Error Rate Test Control Register (BERCR) Bits (continued) MT90870 Description Zarlink Semiconductor Inc. Data Sheet -1 is selected for the selected for the Local selected for the ...
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... Delay Bits Input Stream LCD7-LCD0 0000 0000 1 Channel 0000 0001 2 Channels 0000 0010 3 Channels 0000 0011 4 Channels 0000 0100 5 Channels 0000 0101 ... ... 253 Channels 1111 1101 254 Channels 1111 1110 255 Channels 1111 1111 57 Zarlink Semiconductor Inc. Data Sheet Description ... ... : ...
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... Table 22 - Local Input Bit Delay Programming Table MT90870 Reset Description 0 Reserved 0 Local Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the Local input stream 1 / bit period Corresponding Delay Bits LID3 LID2 Zarlink Semiconductor Inc. Data Sheet LID1 LID0 ...
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... Mb/s streams Mb/s streams Mb/s streams) from the frame boundary. MT90870 Corresponding Delay Bits LID3 LID2 Name Reset 0 Reserved 0 Backplane Channel Delay Register The binary value of these bits refers to the channel delay value for the Backplane input stream 59 Zarlink Semiconductor Inc. Data Sheet LID1 LID0 Description ...
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... BID(4:0) 0 Backplane Input Bit Delay Register The binary value of these bits refers to the input bit delay value for the Backplane input stream Zarlink Semiconductor Inc. Data Sheet BCD8-BCD0 0 0000 0000 0 0000 0001 0 0000 0010 0 0000 0011 0 0000 0100 0 0000 0101 ... ...
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... Sixteen Local output advancement registers (LOAR0 to LOAR15) allow users to program the output advancement for output data streams LSTo0 to LSTo15. The possible adjustment is - cycles of the internal system clock (131.072 MHz). MT90870 Corresponding Delay Bits BID4 BID3 BID2 Zarlink Semiconductor Inc. Data Sheet BID1 BID0 ...
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... Backplane frame pulse. MT90870 Reset 0 Reserved 0 Local Output Advancement Register Corresponding Advancement Bits LOA1 Name Reset Reserved 0 Reserved BOA(1:0) 0 Backplane Output Advancement Register 62 Zarlink Semiconductor Inc. Data Sheet Description LOA0 Description ...
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... The binary value of these bits refers to the Local output stream which carries the BER data. 0 Local BER Send Channel Address Bits. The binary value of these bits refers to the Local output channel in which the BER data starts to be sent. Description 63 Zarlink Semiconductor Inc. Data Sheet Corresponding Advancement Bits BOA1 BOA0 0 0 ...
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... The binary value of these bits refers to the Local input stream to receive the BER data. Local BER Receive Channel Address Bits The binary value of these bits refers to the Local input channel in which the BER data starts to be compared. 64 Zarlink Semiconductor Inc. Data Sheet ...
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... The binary value of these bits define the Backplane output stream to transmit the BER data. Backplane BER Send Channel Address Bits The binary value of these bits define the Backplane output Start Channel in which the BER data is transmitted. Description 65 Zarlink Semiconductor Inc. Data Sheet ...
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... Backplane BER Count Register contains the number of counted errors. This register is read only. The BBCR register is configured as follows: Bit Name Reset 15-0 BBC(15:0) 0 Table 40 - Backplane BER Count Register (BBCR) Bits MT90870 Description Description Description Backplane Bit Error Rate Count The binary value of these bits define the Backplane Bit Error count. 66 Zarlink Semiconductor Inc. Data Sheet ...
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... LOBR1 Table 44 - Output Bit Rate (LOBR) Programming Register MT90870 Description 0 Reserved 0 Local Input Bit Rate LIBR0 Bit rate for stream Mb/s Reset 0 Reserved 0 Local Output Bit Rate LOBR0 Bit rate for stream Mb/s 67 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Reserved 1-0 BOBR(1:0) Table 47 - Backplane Output Bit Rate Register (BOBRRn) Bits MT90870 Reset 0 Reserved 0 Backplane Input Bit Rate BIBR0 Bit rate for stream Mb/s Reset 0 Reserved 0 Backplane Output Bit Rate 68 Zarlink Semiconductor Inc. Data Sheet Description Description ...
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... Sequence enabled on LOW to HIGH transition. 4 BISTCCB 0 Backplane Connection Memory BIST sequence completed. (Read only). High indicates completion of Memory BIST sequence. Table 49 - Memory BIST Register (MBISTR) Bits MT90870 BOBR0 Bit rate for stream 2Mb 4Mb 8Mb 16Mb/s Description 69 Zarlink Semiconductor Inc. Data Sheet ...
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... The revision control register stores the binary value of the silicon revision number. This register is read only. The RCR register is configured as follows: Bit Name Reset Value 15-4 Reserved 3-0 RC(3:0) defined by silicon Table 50 - Revision Control Register (RCR) Bits MT90870 Description 0 Reserved. Revision Control Bits. 70 Zarlink Semiconductor Inc. Data Sheet Description ...
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... DD_PLL V -0 -0.5 I_5V Sym. Min. Typ 3.0 3.3 DD_IO V 1.62 1.8 DD_CORE V 1.62 1.8 DD_PLL I_5V 71 Zarlink Semiconductor Inc. Data Sheet Max. Units 2.5 V 5 +0.5 V DD_IO 7 C +125 Max. Units C +85 3.6 V 1. DD_IO 5.5 V ...
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... Sym. Level Units V 0. DD_IO V 0. DD_IO V 0. DD_IO 72 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions mA Static I and DD_Core PLL current mA Applied clock C8i = 8.192 MHz A Static I DD_IO mA I with all output AV streams at max. data-rate V V A 0 < V < V ...
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... FODF8 t 56 GFPS8 FODR8 t 59 GFPH8 o t 117 LCP8 t 56 LCH8 t 59 LCL8 rLC8o fLC8o t 62 FPW16 t -29 FODF16 t 30 FODR16 73 Zarlink Semiconductor Inc. Data Sheet Notes 350 ns 220 220 110 ns 110 110 110 ns 110 110 124 7.5 ns 127 ns 127 C =60pF ...
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... Backplane and Local Clock Timing (continued) Characteristic 20 C16o Clock Period 21 C16o Clock Pulse Width High 22 C16o Clock Pulse Width Low C16o Clock 23 Rise/Fall Time MT90870 Sym. Min. Typ. Max. Units t 62 LCP16 t 29 LCH16 t 30 LCL16 rLC16o fLC16o 74 Zarlink Semiconductor Inc. Data Sheet Notes =60pF ...
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... CK_int is the internal clock signal of 131.072 MHz Figure 20 - Backplane and Local Clock Timing Diagram for ST-BUS MT90870 t BFPW244 t BFPH244 t BFPW122 t BFPH122 t BCP8 t fBC8i t LFBOS t LFPW8_244 t FODR8_244 t LFPW8 t LFODF8 LFODR8 t t LCH8 LCP8 t rLC8o t FPW16 t FODR16 t LCP16 t rLC16o 75 Zarlink Semiconductor Inc. Data Sheet t rBC8i t fLC8o t fLC16o ...
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... Figure 21 - Backplane and Local Clock Timing for GCI-BUS MT90870 t BGFPW t t BGFPS BGFPH t BCP8 t t BCH8 BCL8 t t fBC8i rBC8i t LFBOS t GFPW8 t t GFPS8o GFPH8o t t LCH8 LCP8 t FPW16 t FRH16o t LCP16 t rLC16o 76 Zarlink Semiconductor Inc. Data Sheet t t rLC8o fLC8o t fLC16o ...
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... BSIS16 2.1 t BSIS8 2.1 t BSIS4 2.1 t BSIS2 t 3 BSIH32 3 t BSIH16 3 t BSIH8 3 t BSIH4 3 t BSIH2 t BSOD32 t BSOD16 t BSOD8 t BSOD4 t BSOD2 77 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes 28 ns With zero 51 offset. 97 188 371 =50pF 10 10.5 10.5 10.5 10.5 ...
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... BSIH4 Bit7 Bit6 Ch0 Ch0 t BSOD4 Bit7 Bit6 Ch0 Ch0 t BIDS2 t BSIS2 t BSIH2 Bit7 Ch0 t BSOD2 Bit7 Ch0 78 Zarlink Semiconductor Inc. Data Sheet Bit2 Bit1 Bit3 Ch0 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit5 Bit4 Ch0 Ch0 Bit6 Ch0 Bit6 Ch0 ...
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... BSIS32 t BSIH32 BSOD32 Bit7 Bit6 Bit5 Bit0 Ch0 Ch0 Ch0 Ch511 t BIDS16 t BSIS16 t BSIH16 Bit0 Bit7 Ch0 t Ch 255 BSOD16 Bit7 Ch0 79 Zarlink Semiconductor Inc. Data Sheet Bit4 Bit2 Bit3 Ch0 Ch0 Ch0 Bit6 Bit5 Ch0 Ch0 Bit5 Bit6 Ch0 Ch0 ...
Page 80
... Bit1 Bit2 Ch0 Ch0 tBSOD4 Bit1 Bit0 Ch0 Ch0 tBIDS2 tBSIS2 tBSIH2 Bit0 Ch0 tBSOD2 Bit0 Ch0 80 Zarlink Semiconductor Inc. Data Sheet Bit5 Bit6 Bit4 Ch0 Ch0 Ch0 Bit3 Bit4 Ch0 Ch0 Bit2 Bit3 Ch0 Ch0 Bit1 Ch0 ...
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... LSIS8 2.1 t LSIS4 2.1 t LSIS2 t 3 LSIH16 t 3 LSIH8 t 3 LSIH4 3 t LSIH2 t LSOD16 t LSOD8 t LSOD4 t LSOD2 81 Zarlink Semiconductor Inc. Data Sheet Bit3 Bit5 Bit4 Ch0 Ch0 Ch0 Bit1 Bit2 Ch0 Ch0 Bit2 Bit1 Ch0 Ch0 Max. Units Notes 7 With zero 97 offset ...
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... Ch0 tLIDS4 tLSIS4 tLSIH4 Bit7 Bit6 Ch0 Ch0 tLSOD4 Bit7 Bit6 Ch0 Ch0 tLIDS2 tLSIS2 tLSIH2 Bit7 Ch0 tLSOD2 Bit7 Ch0 82 Zarlink Semiconductor Inc. Data Sheet Bit5 Bit6 Bit5 Bit6 Ch0 Ch0 Bit2 Bit1 Bit3 Ch0 Ch0 Ch0 Bit5 Bit4 Ch0 ...
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... Hi-Z Hi-Z Figure 29 - Output Driver Enable (ODE) Sym. Min. Typ CSS t 8 RWS t 8 ADS t 0 CSH t 8 RWH 83 Zarlink Semiconductor Inc. Data Sheet Test Conditions R =1K, C =50pF, See Note =1K, C =50pF, See Note =1K, C =50pF, See Note VTT VTT Max. ...
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... DHW t AKD AKH = 1K/1K potential divider, with timing corrected to cancel time L t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t DDR t AKD 84 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns C =60pF =60pF Note =60pF =60pF L ns ...
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