MT90870AG Zarlink, MT90870AG Datasheet - Page 45

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

When a RESET is applied to the MT90870, the CS line is inhibited and the DTA line may become active through
simultaneous microport activity. External gating of the DTA line with CS is recommended to avoid bus conflict in
applications incorporating multiple devices with individual reset conditions.
9.0
Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both ports
there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to
allow either looped back, or uni-directional testing. The transmitter generates a 2
Binary Sequence (PRBS), which may be allocated to a specific stream and a number of channels. This is defined
by a stream number, a start channel number, and the number of consecutive channels following the start channel.
The stream, channel number and the number of consecutive channels following the start channel are similarly
allocated for the receiver and detection of the PRBS. Examples of a channel sequence are presented in Figure 17.
When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved, by
detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter. A
counter ’roll-over’ shall occur in the event of an error count in excess of 65535.
The BER operations are controlled by registers as follows (refer to Section 13.3, Bit Error Rate Test Control
Register (BERCR) for overall control, Section 13.10, Local Bit Error Rate (BER) Registers and Section 13.11,
Backplane Bit Error Rate (BER) Registers for register programming details):
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The registers listed completely define the transmit stream and channels. When BER transmission is enabled for
these channels, the source bits and the message mode bits, LSRC and LMM in the Local Connection Memory, and
BSRC and BMM in the Backplane Connection Memory, are ignored. The enable bits (LE and BE) of the respective
connection memories should be set to HIGH to enable the outputs for the selected channels.
BER Control Register (BERCR) - Independently enables BER transmission and receive testing for
Backplane and Local ports.
Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Defines the output stream and start
channel for BER transmission.
Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Defines, for transmit
stream, how many consecutive channels to follow the start channel.
Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel
from where the BER sequence will start to be compared.
Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Defines, for the receive
stream, how many consecutive channels follow the start channel.
Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
Bit Error Rate Test
Zarlink Semiconductor Inc.
MT90870
45
15
-1 or 2
23
-1 Pseudo Random
Data Sheet