MT90870AG Zarlink, MT90870AG Datasheet - Page 52

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.0
This section describes the registers that are used in the device.
13.1
Address 0000h.
The control register defines which memory is to be accessed. It initiates the memory block programming mode and
selects the Backplane data rate mode. The Control Register (CR) is configured as follows:
15-9
Bit
8
7
6
5
4
3
Control Register (CR)
Reserved
Detailed Register Description
MODE32
C8IPOL
COPOL
Name
FPW
MBP
OSB
Reset
0
0
0
0
0
0
0
Reserved.
Frame Pulse Width
When LOW, an input frame pulse width of 122 ns shall be applied to FP8i. When
HIGH, an input frame pulse width of 244 ns shall be applied to FP8i.
32 MHz Mode
When LOW, Backplane streams (BSTi0-31 and BSTo0-31) may be individually
programmed for data-rates of 2, 4, 8, or 16 Mb/s. When HIGH, the Backplane
streams (BSTi0-15 and BSTo0-15) operate in 32Mb/s mode.
8 MHz Input Clock Polarity
The input frame boundary MUST be aligned to the C8i clock rising edge. This bit,
C8IPOL, MUST be set HIGH to achieve correct frame boundary alignment. If this
bit is LOW, the input frame boundary alignment will not work correctly.
Output Clock Polarity
When set LOW, the output clock is the same polarity as the input clock. When set
HIGH, the output clock is inverted. This applies to both 8 MHz (C8o)and 16 MHz
(C16o) output clocks.
Memory Block Programming
When LOW, the memory block programming mode is disabled. When HIGH, the
connection memory block programming mode is ready to program the Local
Connection Memory (LCM), and the Backplane Connection Memory (BCM).
Output Stand By
This bit enables the BSTo0 - 31 and the LSTo0 - 15 serial outputs.
When set LOW, the BSTo0-31 and LSTo0-15 are driven high or high impedance,
dependent on the BORS and LORS pin settings respectively, and BCSTo0-3 and
LCSTo0-1 are driven low.
When set HIGH, the BSTo0-31, LSTo0-15, BCSTo0-3 and LCSTo0-1 are enabled.
ODE Pin
Table 16 - Control Register Bits
0
1
1
Zarlink Semiconductor Inc.
Output Control with ODE pin and OSB bit
MT90870
OSB bit
52
X
0
1
Description
BSTo0 - 31, LSTo0 - 15
Disable
Disable
Enable
Data Sheet