MT90870AG Zarlink, MT90870AG Datasheet - Page 55

• Manufacturer Part Number: MT90870AG
• Description: Switch Fabric 12K x 12K/8K x 4K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90870AG

• Package: 272BGA
• Number Of Ports: 32
• Fabric Size: 12K x 12K|8K x 4K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.3
Address 0002h.
The BER control register controls Backplane and Local port BER testing. It independently enables and disables
transmission and reception. It is configured as follows:
15-7
15-12
6-4
3-1
Bit
Bit
0
11
10
9
Bit Error Rate Test Control Register (BERCR)
BBPD(2:0)
LBPD(2:0)
Reserved
LOCKB
PRSTB
CBERB
Unused
Name
BPE
Name
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits
Reset
RESET
0
0
0
0
0
0
0
0
Set LOW.
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW.
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW.
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 us, upon completion of programming.
Set LOW to abort the programming operation.
Table 17 - Block Programming Register Bits
Reserved.
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
PBER Reset for Backplane.
A LOW to HIGH transition initializes the Backplane BER generator to the
seed value.
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane bit error (BBERR) register to zero.
Zarlink Semiconductor Inc.
MT90870
55
Description
Description
Data Sheet