PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 72

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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3.0 General-Purpose Input/Output (GPIO) Port
Note: This section applies to the PC87392, PC87393 and PC87393F only.
This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.
For the device specific implementation, see the Device Architecture and Configuration chapter.
3.1 OVERVIEW
The GPIO port is an 8-bit port, which is based on eight pins. It features:
GPIO port operation is associated with two sets of registers:
Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as
shown in Figure 8.
The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO
pins, and enhanced functionality. The basic functionality is described in Section 3.2. The enhanced functionality which in-
cludes the event detection and system notification is described in Section 3.3.
Configuration (GPCFG)
Routing (GPEVR)
GPIO Pin Event
Software capability to manipulate and read pin levels
Controllable system notification by several means based on the pin level or level transition
Ability to capture and manipulate events and their associated status
Back-drive protected pins.
Pin Configuration registers, mapped in the Device Configuration space. These registers are used to statically set up
the logical behavior of each pin. There are two 8-bit register for each GPIO pin.
Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and
GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by
the base address registers in the GPIO Device Configuration). They are used to manipulate and/or read the pin val-
ues, and to control and handle system notification. Each runtime register corresponds to the 8-pin port, such that bit
n in each one of the four registers is associated with GPIOXn pin, where X is the port number.
Select (GPSEL)
X = port number
n = pin number, 0 to 7
GPIO Pin
Register
Register
GPIO Pin
Register
Port and Pin
Select
Figure 8. GPIO Port Architecture
GPIOX Base Address
GPIOXn ROUTE
GPIOXn CNFG
8 GPEVR
8 GPCFG
Registers
Registers
72
Event
Pending
Indicator
Port Logic
GPIOXn
Bit n
x8
Routing
Control
Event
GPDOX
GPDIX
GPEVENX
GPEVSTX
x8
GPIOXn
Registers
Runtime
Pin
Interrupt
Request
SMI
x8