PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 52

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

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2.0 Device Architecture and Configuration
2.12.3 Parallel Port Configuration Register
This register is reset by hardware to F2h.
Location:
Type:
Bit
Name
Reset
7-5
Bit
4
3
2
1
0
Parallel Port Mode Select
000:
001:
010:
011:
100:
101:
110:
111:
Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2 configuration register of the
parallel port at offset 02h.
Extended Register Access
0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).
1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-
Reserved
PP Reflected Input Signals. When the parallel port input signal is disconnected by the PPM, the input signals
reflected by the STR register assume one of the following values:
0: BUSY = 1, PE = 0, SLCT = 0, ACK = 1 (default)
1: BUSY = 1, PE = 1, SLCT = 1, ACK = 1.
Power Mode Control. When the logical device is active:
0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active.
1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default).
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disabled (default)
1: Enabled
time configuration within the Parallel Port address space.
Registers are maintained.
Index F0h
R/W
SPP Compatible mode. PD7-0 are always output signals.
SPP Extended mode. PD7-0 direction is controlled by software.
EPP 1.7 mode
EPP 1.9 mode
ECP mode (IEEE1284 register set), with no support for EPP mode.
Reserved
Reserved
ECP mode (IEEE1284 register set), with EPP mode selectable as mode 4.
7
1
Parallel Port Mode Select
6
1
5
1
Extended
Register
Access
Description
52
4
1
(Continued)
Reserved
3
0
PP Reflect-
ed Input
Signals
2
0
Control
Power
Mode
1
1
TRI-STATE
Control
0
0