PC87393VJG National Semiconductor, PC87393VJG Datasheet - Page 7

• Manufacturer Part Number: PC87393VJG
• Description: IC, SUPER I/O DEVICE, TQFP-100
• Manufacturer: National Semiconductor

Specifications of PC87393VJG

• Data Rate: 2Mbps
• Supply Voltage Range: 3V to 3.6V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C to +70°C
• Termination Type: SMD
• Transceiver Type: Interface
• Rohs Compliant: No

Table of Contents
3.0
4.0
2.17
2.18
2.19
General-Purpose Input/Output (GPIO) Port
3.1
3.2
3.3
3.4
WATCHDOG Timer (WDT)
4.1
4.2
4.3
GAME PORT (GMP) CONFIGURATION .................................................................................. 62
2.17.1
2.17.2
MIDI PORT (MIDI) CONFIGURATION ...................................................................................... 64
2.18.1
2.18.2
X-BUS CONFIGURATION ......................................................................................................... 65
2.19.1
2.19.2
2.19.3
2.19.4
2.19.5
2.19.6
2.19.7
2.19.8
2.19.9
2.19.10 X-Bus Memory Base Address Low Byte Register ....................................................... 70
2.19.11 X-Bus Memory Size Configuration Register ................................................................ 70
2.19.12 X-Bus PIRQA and PIRQB Mapping Register .............................................................. 71
2.19.13 X-Bus PIRQC and PIRQD Mapping Register .............................................................. 71
OVERVIEW ............................................................................................................................... 72
BASIC FUNCTIONALITY .......................................................................................................... 73
3.2.1
3.2.2
EVENT HANDLING AND SYSTEM NOTIFICATION ................................................................ 74
3.3.1
3.3.2
GPIO PORT REGISTERS ......................................................................................................... 75
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
OVERVIEW ............................................................................................................................... 80
FUNCTIONAL DESCRIPTION .................................................................................................. 80
WATCHDOG TIMER REGISTERS ........................................................................................... 81
4.3.1
4.3.2
4.3.3
Logical Device 11 (GMP) Configuration ...................................................................... 62
Game Port Configuration Register .............................................................................. 62
Logical Device 12 (MIDI) Configuration ....................................................................... 64
MIDI Port Configuration Register ................................................................................. 64
Logical Device 15 (X-Bus) Configuration ..................................................................... 65
X-Bus I/O Range Programming ................................................................................... 65
X-Bus Memory Range Programming ........................................................................... 66
X-Bus I/O Configuration Register ................................................................................ 66
X-Bus I/O Base Address High Byte Register ............................................................... 68
X-Bus I/O Base Address Low Byte Register ............................................................... 68
X-Bus I/O Size Configuration Register ........................................................................ 68
X-Bus Memory Configuration Register ........................................................................ 69
X-Bus Memory Base Address High Byte Register ...................................................... 69
Configuration Options .................................................................................................. 73
Operation ..................................................................................................................... 73
Event Configuration ..................................................................................................... 74
System Notification ...................................................................................................... 74
GPIO Pin Configuration (GPCFG) Register ................................................................ 76
GPIO Pin Event Routing (GPEVR) Register ............................................................... 77
GPIO Port Runtime Register Map ............................................................................... 77
GPIO Data Out Register (GPDO) ................................................................................ 78
GPIO Data In Register (GPDI) .................................................................................... 78
GPIO Event Enable Register (GPEVEN) .................................................................... 79
GPIO Event Status Register (GPEVST) ...................................................................... 79
WATCHDOG Timer Register Map ............................................................................... 81
WATCHDOG Timeout Register (WDTO) .................................................................... 81
WATCHDOG Mask Register (WDMSK) ...................................................................... 82
(Continued)
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