P80C592FFA NXP Semiconductors, P80C592FFA Datasheet - Page 70

• Manufacturer Part Number: P80C592FFA
• Manufacturer: NXP Semiconductors

Specifications of P80C592FFA

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: CAN/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 512Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
16 OSCILLATOR CIRCUITRY
The oscillator circuitry of the P8xC592 is a single-stage
inverting amplifier in a Pierce oscillator configuration. The
circuitry between XTAL1 and XTAL2 is basically an
inverter biased to the transfer point. Either a crystal or
ceramic resonator can be used as the feedback element to
complete the oscillator circuitry. Both are operated in
parallel resonance. XTAL1 (pin 34) is the high gain
amplifier input, and XTAL2 (pin 33) is the output
(see Fig.23). If XTAL1 is driven from an external source,
XTAL2 must be left open (see Fig.24).
17 RESET CIRCUITRY
The reset pin RST is connected to a Schmitt trigger for
noise rejection (see Fig.25). A reset is accomplished by
holding the RST pin HIGH for at least two machine cycles
(24 oscillator periods). The CPU responds by executing an
internal reset. During reset ALE and PSEN output a HIGH
level. In order to perform a correct reset, this level must not
be affected by external elements.
Also with the P8xC592, the RST line can be pulled HIGH
internally by a pull-up transistor activated by the Watchdog
timer T3. The length of the output pulse from T3 is
3 machine cycles. A pulse of such short duration is
necessary in order to recover from a processor or system
fault as fast as possible.
During Power-down a reset could be generated internally
via the CAN Wake-Up interrupt. Then the RST pin is pulled
HIGH for 6144 machine cycles. In this case the
CAN-controller is not reset.
If the Watchdog timer or the CAN Wake-Up interrupt is
used to reset external devices, the usual capacitor
arrangement for Power-on-reset (see Fig.26) should not
be used.
However, the internal reset is forced, independent of the
external level on the RST pin.
The MAIN RAM and AUXILIARY RAM are not affected.
When V
A reset leaves the internal registers as shown in Table 83.
1996 Jun 27
8-bit microcontroller with on-chip CAN
DD
is turned on, the RAM content is indeterminate.
70
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handbook, halfpage
Fig.24 Driving P8xC592 from an external source.
RST
(not TTL compatible)
V DD
external clock
Fig.25 On-chip reset configuration.
R
on-chip
Fig.23 P8xC592 oscillator circuit.
RST
not connected
20 pF
20 pF
C2
C1
MLA888
MLA889
XTAL1
XTAL2
XTAL1
XTAL2
Product specification
overflow timer T3
wake-up reset
CAN
CPU
P8xC592
34
33
34
33
MGA170 - 1