CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 5

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

CYNSE70064A
LIST OF FIGURES
(continued)
Figure 10-42. Timing Diagram for Globally Winning Device in Block Number 2 ................................... 63
Figure 10-43. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................... 64
Figure 10-44. Timing Diagram for Devices Above the Winning Device in Block Number 3 .................. 65
Figure 10-45. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 66
Figure 10-46. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 30 (the Last Device)....................................................................................................... 67
Figure 10-47. Timing Diagram for Device Number 6 in Block Number 3 (Device 30 in
Depth-Cascaded Table)......................................................................................................................... 68
Figure 10-48. ×136 Table with 31 Devices ............................................................................................ 69
Figure 10-49. Timing Diagram for 272-bit Search (One Device) ........................................................... 70
Figure 10-50. Hardware Diagram for a Table with One Device ............................................................. 70
Figure 10-51. ×272 Table with One Device ........................................................................................... 71
Figure 10-52. Hardware Diagram for a Table with Eight Devices.......................................................... 73
Figure 10-53. Timing Diagram for 272-bit Search Device Number 0..................................................... 74
Figure 10-54. Timing Diagram for 272-bit Search Device Number 1..................................................... 75
Figure 10-55. Timing Diagram for 272-bit Search Device Number 7 (Last Device) .............................. 76
Figure 10-56. ×272 Table with Eight Devices ........................................................................................ 77
Figure 10-57. Hardware Diagram for a Table with 31 Devices .............................................................. 79
Figure 10-58. Hardware Diagram for A Block of up to Eight Devices .................................................... 80
Figure 10-59. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ................. 81
Figure 10-60. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ........... 82
Figure 10-61. Timing Diagram for Globally Winning Device in Block Number 1 ................................... 83
Figure 10-62. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................... 84
Figure 10-63. Timing Diagram for Devices Above the Winning Device in Block Number 2 .................. 85
Figure 10-64. Timing Diagram for Globally Winning Device in Block Number 2 ................................... 86
Figure 10-65. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................... 87
Figure 10-66. Timing Diagram for Devices Above the Winning Device in Block Number 3 .................. 88
Figure 10-67. Timing Diagram for Globally Winning Device in Block Number 3 ................................... 89
Figure 10-68. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device 30 (the Last Device)....................................................................................................... 90
Figure 10-69. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table)............ 91
Figure 10-70. ×272 Table with 31 Devices ............................................................................................ 92
Figure 10-71. Timing Diagram for Mixed Search (One Device)............................................................. 93
Figure 10-72. Multiwidth Configurations Example ................................................................................. 93
Figure 10-73. Timing Diagram of Learn (TLSZ = 00)............................................................................. 95
Figure 10-74. Timing Diagram of Learn (Except on the Last Device [TLSZ = 01])................................ 96
Figure 10-75. Timing Diagram of Learn on Device Number 7 (TLSZ = 01)........................................... 97
Figure 11-1. Depth-Cascading to Form a Single Block ......................................................................... 99
Figure 11-2. Depth-Cascading Four Blocks......................................................................................... 100
Figure 11-3. Full Generation in a Cascaded Table.............................................................................. 101
Figure 12-1. SRAM Read Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)........................... 103
Figure 12-2. Table of a Block of Eight Devices.................................................................................... 104
Figure 12-3. SRAM Read Through Device Number 0 in a Block of Eight Devices.............................. 105
Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices ........................... 106
Figure 12-5. Table of 31 Devices Made of Four Blocks....................................................................... 107
Figure 12-6. SRAM Read Through Device Number 0 in a Bank of 31 Devices
(Device Number 0 Timing)................................................................................................................... 108
Figure 12-7. SRAM Read Through Device Number 0 in Bank of 31 Devices
(Device Number 30 Timing)................................................................................................................. 109
Document #: 38-02041 Rev. *F
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