CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 13

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

6.0
CYNSE70064A receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate an internal
CLK, as shown in Figure 6-1. The CYNSE70064A uses CLK for internal operations. Also noted on these figures are cycles A and
cycle B. Cycle A ends on the rising edge of CLK2X, when PHS_L is high. Cycle B ends on the rising edge of the CLK2X when
PHS_L is low. Valid data for cycle A must be available for the NSE at the end of cycle A. Valid data for cycle B must be available
for the NSE at the end of cycle B. PHS_L has setup and hold times requirements with respect to CLK2X. The setup and hold
time requirements can be referred to in Section 17.0, AC Timing Waveforms.
7.0
All registers in the CYNSE70064A are 68 bits wide. The CYNSE70064A contains 16 pairs of comparand storage registers, eight
pairs of GMRs, eight search successful index registers and one each of CMD, information, burst Read, burst Write, and next-free
address registers. Table 7-1 provides an overview of all the CYNSE70064A registers. The registers are ordered in ascending
address order. Each register group is then described in the following subsections.
Table 7-1. Register Overview
7.1
The device contains 32 68-bit comparand registers (16 pairs) dynamically selected in every Search operation to store the
comparand presented on the DQ bus. The Learn command will later use these registers when executed. The CYNSE70064A
stores the Search command’s cycle A comparand in the even-numbered register and the cycle B comparand in the odd-numbered
register, as shown in Figure 7-1.
Document #: 38-02041 Rev. *F
Address
32–47
48–55
61–63
0–31
56
57
58
59
60
Comparand Registers
Clocks
Registers
Input Data
CLK
CLK2X
PHS_L
Abbreviation
COMMAND
COMP0–31
WBURREG
RBURREG
SSR0–7
MASKS
INFO
NFA
–
“Cycle A End”
Figure 6-1. CYNSE70064A Clocks (CLK2X and PHS_L)
Type
RW
RW
RW
RW
R
R
R
R
–
A
“Cycle B End”
Sixteen pairs of comparand registers that store comparands from the
DQ bus for learning later.
Eight global mask register pairs.
Eight search successful index registers.
Command register.
Information register.
Burst Read register.
Burst Write register.
Next-free address register.
Reserved.
B
Name
CYNSE70064A
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