CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 106

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.5
The following explains the SRAM Read operation accomplished through a table of up to 31 devices, using the following param-
eters: TLSZ = 10. The diagram of such a table is shown in Figure 12-5. The following assumes that SRAM access is being
accomplished through CYNSE70064A device number 0, that device number 0 is the selected device. Figure 12-6 and Figure 12-7
show the timing diagrams for device number 0 and device number 30, respectively.
At the end of cycle 10, the selected device floats ACL in a three-state condition.
Document #: 38-02041 Rev. *F
• Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycles 5 to 6: The selected device continues to drive DQ[67:0].
• Cycle 7: The selected device continues to drive DQ[67:0] and drives an SRAM Read cycle.
• Cycle 8: The selected device drives ACL from Z to LOW.
• Cycle 9: The selected device drives ACK to HIGH.
• Cycle 10: The selected device drives ACK from HIGH to LOW.
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[21:20] on CMD[8:7].
address, with DQ[20:19] set to 10, to select the SRAM address.
SRAM Read with a Table of up to 31 Devices
CMD[8:2]
TLSZ = 01, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 12-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices
CMD[1:0]
CLK2X
ALE_L
PHS_L
CMDV
SSV
SADR
ACK
CE_L
SSF
WE_L
OE_L
DQ
0
1
1
1
z
z
z
z
cycle
1
Address
A
Read
B
cycle
2
z
cycle
3
cycle
4
cycle
5
cycle
6
z
z
z
z
CYNSE70064A
1
1
1
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