CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 23

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Figure 10-4 shows the timing diagram of a burst Write operation of the data or mask array.
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG register. The following is the block Write operation sequence. This operation assumes that the host ASIC
has programmed the WBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating a burst Write
command.
The CYNSE70064A writes the data on the DQ[67:0] bus only to the subfield that has the corresponding mask bit set to 1 in the
GMR specified by the index CMD[5:3] supplied in cycle 1. The CYNSE70064A drives the EOT signal LOW from cycle 3 to cycle
n; the CYNSE70064A drives the EOT signal HIGH in cycle n + 1 (n is specified in the BLEN field of the WBURREG).
At the termination of cycle n + 2, the CYNSE70064A floats the EOT signal to a three-state operation, and a new instruction can
begin.
Table 10-9. Write Address Format for Data and Mask Array (Burst Write)
Document #: 38-02041 Rev. *F
• Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied
• Cycle 1B: The host ASIC continues to apply the Write instruction on the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data or mask array location of the selected device.
• Cycles 3 to n + 1: The host ASIC drives the DQ[67:0] with the data to be written to the next data or mask array location
• Cycle n + 2: TheCYNSE70064A drives the EOT signal LOW.
DQ[67:26]
on the DQ bus, as shown in Table 10-9. The host ASIC also supplies the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3]. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects all the
devices when DQ[25:21] = 11111.
The CYNSE70064A writes the data from the DQ[67:0] bus only to the subfield that has the corresponding mask bit set to 1 in
the GMR specified by the index CMD[5:3] supplied in cycle 1.
(addressed by the auto-increment ADR field of the WBURREG register) of the selected device.
Reserved
Reserved
DQ[25:21]
CMD[1:0]
CMD[8:2]
CLK2X
PHS_L
CMDV
ID
ID
EOT
DQ
Figure 10-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
01: Mask array
00: Data array
DQ[20:19]
Address
cycle
A
Write
1
B
cycle
DQ[18:15]
Reserved
Reserved
2
Data0 Data1 Data2
cycle
3
Do not care. These 15 bits come from the internal
register (WBURADR), which increments with each
access.
Do not care. These 15 bits come from the internal
register (WBURADR), which increments with each
access.
cycle
4
cycle
5
Data3
cycle
6
X
DQ[14:0]
CYNSE70064A
Page 23 of 128