CYNSE70064A-50BGC Cypress Semiconductor Corp, CYNSE70064A-50BGC Datasheet - Page 19

• Manufacturer Part Number: CYNSE70064A-50BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-50BGC

• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

10.2
Table 10-2 lists the CMD bus fields that contain the CYNSE70064A command parameters and their respective cycles. Each
command is described separately in the subsections that follow.
Table 10-2. Command Parameters
10.3
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst
Read of the data (CMD[2] = 1) or mask array locations using an internal auto-incrementing address register (RBURADR).
A description of each type is provided in Table 10-3. A single-location Read operation lasts six cycles, as shown in Figure 10-1.
The burst Read adds two cycles for each successive Read. The SADR[21:20] bits supplied in the Read instruction cycle A drives
SADR[21:20] signals during the Read of an SRAM location.
Table 10-3. Read Command Parameters
The single Read operation takes six clock cycles, in the following sequence.
At the termination of cycle 6, the selected device releases the ACK line to three-state condition. The Read instruction is complete,
and a new operation can begin. Note that the latency of the SRAM Read will be different than the one described above (see
Subsection 12.2, “SRAM PIO Access” on page 102). Table 10-4 lists and describes the format of the Read address for a data
array, mask array, or SRAM.
Document #: 38-02041 Rev. *F
CMD Parameter CMD[2]
• Cycle 1: The host ASIC applies the Read instruction on the CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the DQ bus supplies
• Cycle 2: The host ASIC floats DQ[67:0] to three-state condition
• Cycle 3: The host ASIC keeps DQ[67:0] in three-state condition
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives the ACK signal from Z to LOW.
• .Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
• Cycle 6: The selected device floats the DQ[67:0] to three-state condition and drives the ACK signal LOW.
the address, as shown in Table 10-4 and Table 10-5. The host ASIC selects the CYNSE70064A for which ID[4:0] matches the
DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set. The host ASIC
also supplies SADR[21:20] on CMD[8:7] in cycle A of the Read instruction if the Read is directed to the external SRAM.
signal HIGH.
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CMD
Read
Write
Commands and Command Parameters
Read Command
0
1
CYC
A
A
B
B
A
B
A
B
SADR[21]
SADR[21]
SADR[21]
SADR[21]
8
0
0
0
Read Command
Single Read
Burst Read
SADR[20]
SADR[20]
SADR[20]
SADR[20]
SSRI[2:0]
7
0
0
0
1: 136-bit
Reads a single location of the data array, mask array, external SRAM, or
device registers. All access information is applied on the DQ bus.
Reads a block of locations from the data array, or mask array as a burst.
The internal register (RBURADR) specifies the starting address and the
length of the data transfer from the data or mask array, and it auto-incre-
ments the address for each access. All other access information is
applied on the DQ bus. Note. The device registers and external SRAM
can only be read in single-Read mode.
0: 68-bit
Mode
6
0
0
x
x
x
x
GMR Index [2:0]
GMR Index [2:0]
GMR Index 2:0]
5
0
0
Comparand Register Index
Comparand Register Index
Comparand Register Index
4
0
0
3
0
0
Description
68-bit or 136-bit: 0
0 in second cycle
1 in first cycle
0 = Single
0 = Single
0 = Single
0 = Single
1 = Burst
1 = Burst
1 = Burst
1 = Burst
272-bit:
2
CYNSE70064A
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1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1