CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 8

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
APS Port
POSIC2GVC provides a 16-bit APS port for 1+1 protection.
The support of a main and standby PHY interface connectivity
allows several different APS implementation options using
POSIC2GVC.
Multi-Framer APS Implementation
Two POSIC2GVC devices can be connected to two different
transceivers, optics and fibers. POSIC2GVC enables
protection switching with only one device being main and
connected to link layer. The standby POSIC2GVC device is
connected to the main POSIC2GVC device and it is controlled
by host CPU. POSIC2GVC provides APS byte information to
the host CPU. The host CPU is expected to take a protection
switching decision and provide necessary instructions to both
POSIC2GVC devices.
In case of protection switching, in the transmit direction, the
main POSIC2GVC will perform all other operations as
programmed, except some of the line and section processing
of SONET/SDH framing. The main POSIC2GVC device will
then pass on the SPEs to the standby device through the APS
port. The standby device will then perform the rest of the line
and section processing and transport SONET/SDH frames
over standby fiber.
Similarly, in case of protection switched mode, on the receive
side, the standby device will process some of the line and
section overhead and transfer the frames to main device
through the APS port. The main device will perform the rest of
the processing in the receive side.
Single Framer APS Implementation
A main and slave PHY device can be interfaced directly to the
main and APS ports of a single POSIC2GVC device. In this
case, the main PHY is connected to the main line interface and
the standby PHY is connected to the APS port.
CONFIDENTIAL
In the POSIC2GVC transmit path, SONET/SDH data is
bridged across the main and APS ports (per linear 1+1 APS
requirements). When protection switching, POSIC2GVC can
be programmed to switch line inputs from the main receive port
to the APS receive port, or vice versa.
This APS scheme provides solely optical/PHY link level
protection.
PHY STANDBY
PHY MAIN
Figure 5. POSIC2GVC APS Implementation using
TxS
RxM
TxM
RxS
Working Channel
Protection
Two POSIC Devices
RxS
RxM
POSIC STANDBY
TxS
RxS
RxM
TxS
TxM
POSIC MAIN
CY7C9536B
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LINK LAYER
DEVICE