CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 11

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Pin Description
RXFRAME_PULSE
TXFRAME_PULSE
RXD[31:0]
RXCLK
RXCLKs
TXCLKOUT
TXCLKI
TXD[31:0]
SONETTX_PAROU
T
SONETRX_PARIN
LFI_n
Clk2MHz
Clk16MHz
TE1STROBE
TE2STROBE
TPOHSTART
TOHSDIN
POHSDIN
RE1STROBE
RE2STROBE
RPOHSTART
TOHSDOUT
Line Interface Signals
Overhead Bytes Access—Serial Ports
Signal Name
I/O
O HSTL/LVTTL
O HSTL/LVTTL
O HSTL/LVTTL
O HSTL/LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
O LVTTL
I
I
I
I
I
I
I
I
I
HSTL/LVTTL
/LVPECL
HSTL/LVTTL
/LVPECL
HSTL/LVTTL
/LVPECL
HSTL/LVTTL
/LVPECL
HSTL/LVTTL
/LVPECL
HSTL/LVTTL
/LVPECL
LVTTL
LVTTL
LVTTL
Pad Type
1
1
32
1
1
1
1
32
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Pins JTAG
CONFIDENTIAL
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Optional frame pulse input for line interface. Active HIGH.
Frame pulse output for line interface. Active HIGH.
32-bit single ended receive data bus for SONET/SDH link. This bus
can be configured as two 16-bit buses in APS operation.
Receive clock input from the PHY device for line interface.
Receive clock input from the Slave PHY device for SONET/SDH
link to support APS.
Transmit Clock to physical layer device for line interface. This will
be RXCLK or the TXCLKI based on the clock selection in the SONET
Tx block register. During loopback this is same as the RXCLK.
Input transmit clock from physical layer device for line interface.
32-bit single ended transmit data bus for line interface. This bus
can be configured as two 16-bit buses in APS operation.
SONET Tx Parity Output. Can be ODD/EVEN parity, as programmed
in the SONET/SDH Tx block register.
SONET Rx Parity Input. Can be ODD/EVEN parity, as programmed
in the SONET/SDH Rx block register.
Line fault indicator.
When LOW, this signal indicates that the PHY has detected Loss of
Optical signal on the SONET/SDH link.
TOH Serial Port Clock Output. TOHDout is clocked out on rising
edge of this clock and TOHDin is latched-in with falling edge of this
clock. The frequency is 2.048 MHz, derived from SysClk.
POH Serial Port Clock Output. POHDout is clocked out on rising
edge of this clock and POHDin is latched-in with falling edge of this
clock. The frequency is 16.625 MHz, derived from SysClk
Transmit E1 Strobe. Transmit TOH serial port data start indication.
Active HIGH pulse generated once in every 125 ms. Indicates the first
bit of E1 Byte.
Transmit E2 Strobe. Active HIGH pulse generated once in every
125 ms. Indicates the first bit of E2 Byte.
Transmit POH Serial Port Data Start Indication. Active HIGH pulse
generated once in every 125 ms.
Transport over head serial port data input.
Path over head serial port data input.
Receive E1 Strobe. Receive TOH serial port data start indication.
Active HIGH pulse generated once in every 125 ms. Indicates that the
POSIC2GVC expects the first bit of the first byte of E1 should
accompany the next clock edge. MSB is transmitted first.
Receive E2 Strobe. Active HIGH pulse generated once in every 125
ms. Indicates that the POSIC2GVC expects the first bit of the first byte
of E2 should accompany the next clock edge. MSB is transmitted first.
Receive POH Serial Port Data Start Indication. Active HIGH pulse
generated once in every 125 ms. Indicates that the POSIC2GVC
expects the first bit of the first byte of RPOH should accompany the
next clock edge.
Transport over head serial port data output.
Pin Description
CY7C9536B
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