CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 36

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Table 15.CPU System Interface Timing Parameter Values
Table 16.TOH Serial Interface Receive Timing Parameter Values
Table 17.POH Serial Interface Receive Timing Parameter Values
f
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYSCLK
SYSCLKD
CpuClk
CpuAdsS
CpuAdsH
CpuADS
CpuADH
CpuADZ
CpuADO
CpuWrRdS
CpuWrRdH
CpuTaO
CpuBlastS
CpuBlastH
CpuSelS
CpuSelH
CpuIntO
Clk2MHzH
Clk2MHzL
Clk2MHzR
Clk2MHzF
REPW
REO
TOHSDOUTO
Clk16MHzH
Clk16MHzL
Clk16MHzR
Clk16MHzF
RPOHPW
RPOHO
POHSDOUTO
Parameter
Parameter
Parameter
[22]
[21]
[21]
[21]
[22]
[21]
[21]
[22]
[21]
[22]
[21]
[22]
[21]
[22]
SYSCLK Frequency
SYSCLK Duty Cycle
CpuClk Freq.
CpuAds_n Set-up Time to CpuClk
CpuAds_n Hold Time to CpuClk
CpuAD Set-up Time to CpuClk
CpuAD Hold Time to CpuClk
CpuAD Float
CpuAD Output Delay after CpuClk Rise
CpuWrRd Set-up Time to CpuClk
CpuWrRd Hold Time to CpuClk
CpuTa_n Valid Delay
CpuBlast_n Set-up to CpuClk
CpuBlast_n Hold to CpuClk
CpuSel Set-up to CpuClk
CpuSel Hold to CpuClk
CpuInt Valid Delay
Clk2MHz Low Period
Clk2MHz Rise Time
Clk2MHz Fall Time
RE1STROBE or RE2STROBE Output Delay after Clk2MHZ
Rising Edge
TOHSDOUT Output Delay after Clk2MHZ Rising Edge
Clk16MHz High Period
Clk16MHz Low Period
Clk16MHz Rise Time
Clk16MHz Fall Time
RPOHSTART Pulse Width
RPOHSTART Output Delay after Clk16MHZ Rising Edge
POHSDOUT Output Delay after Clk16MHZ Rising Edge
Clk2MHz High Period
RE1STROBE or RE2STROBE Pulse Width
Description
Description
Description
CONFIDENTIAL
Min.
Min.
Min.
133
45
31
31
62
–
7
2
7
2
–
–
7
2
–
7
2
7
2
–
–
–
–
–
3
3
–
–
7
–
–
133.33
Max.
Max.
Max.
10.1
10.1
10.1
55
66
14
34
34
67
–
–
–
–
–
–
–
–
–
–
6
6
8
8
5
5
6
6
9
8
8
CY7C9536B
[27]
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SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
cycles
cycles
cycles
cycles
cycles
cycles
MHz
MHz
Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%