CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 13

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Pin Description
RDAT[31:0]
RADD[7:0]
RMOD[1:0]
RPRTY
Signal Name
(continued)
I/O
O LVTTL
O LVTTL
O LVTTL
O LVTTL
Pad Type
32
8
2
1
Pins JTAG
CONFIDENTIAL
N
N
N
N
POS:
Receive Packet Data Bus (RDAT[31:0])
The RDAT[31:0] bus carries the packet octets that are read from the
receive FIFO and the in-band port address of the selected receive
FIFO. RDAT[31:0] is considered valid only when RVAL is asserted.
Given the defined data structure, bit 31 is received first and bit 0 is
received last.
ATM:
Receive Cell Data Bus (RxData[31:0])
The RDAT[31:0] bus carries the Cell octets that are read from the
receive FIFO. RDAT[31:0] is considered valid only when RENB is
asserted. Given the defined data structure, bit 31 is received first and
bit 0 is received last
RDAT[31:0] is updated on the rising edge of RCLK. This bus is
big-endian in format.
HBST:
Receive Data Bus (RDATA[31:0])
32-bit Data Bus, the data is valid when RDVAL signal is active.
HBST:
Receive Port Address (RADDR[7:0]).
When RDVAL signal is active, this address on this bus indicates port
address in RADDR[3:0] and tag value in RADDR[7:4]. In
single-channel mode all 8 bits will contain the tag value. RADDR is
considered valid only when RDVAL is asserted
POS:
Receive Word Modulo (RMOD[1:0]) signal.
RMOD[1:0] indicates the number of valid bytes of data in RDAT[31:0].
The RMOD bus should always be all zero, except during the last
double-word transfer of a packet on RDAT[31:0]. When REOP is
asserted, the number of valid packet data bytes on RDAT[31:0] is
specified by RMOD[1:0]
RMOD[1:0] = “00” RDAT[31:0] valid
RMOD[1:0] = “01” RDAT[31:8] valid
RMOD[1:0] = “10” RDAT[31:16] valid
RMOD[1:0] = “11” RDAT[31:24] valid
RMOD[1:0] is considered valid only when RVAL is asserted.
In 16-bit mode, only RMOD[0] is valid.
RMOD[0] = “1” RDAT[15:8] valid (16-bit mode)
RMOD[0] = “0” RDAT[15:0] valid (16-bit mode)
HBST:
Receive Data Byte Valid (RBVAL[1:0]) signals.
This indicates the number of bytes data bytes valid on the RDATA bus,
00 = 4 bytes valid, 11 = 1 byte valid.
POS:
Receive Parity (RPRTY) signal.
The receive parity (RPRTY) signal indicates the parity calculated over
the RDAT bus. RPRTY supports both odd and even parity.
ATM:
Receive Parity (RxPrty) signal.
Data bus odd parity.
HBST:
Receive bus parity (RPARITY) signal.
Receive bus parity, Even/Odd parity calculated on the data bus alone
or on all the bus signals (RDATA, RADDR, RDVAL, RBVAL, RSOP,
REOP, RERR).
Pin Description
CY7C9536B
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