CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet - Page 15

• Manufacturer Part Number: CY7C9536B-BLC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9536B-BLC

• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-02078 Rev. *G
Pin Description
TFCLK
TERR
TENB
Signal Name
(continued)
I/O
I
I
I
LVTTL
LVTTL
LVTTL
Pad Type
1
1
1
Pins JTAG
CONFIDENTIAL
N
N
N
POS:
Transmit FIFO Write Clock (TFCLK).
TFCLK is used to synchronize data transfer
transactions between the LINK Layer device and POSIC2GVC.
TFCLK may cycle at a rate up to 100 MHz.
ATM:
Transfer/interface clock (TxClk).
HBST:
Transmit Clock (TCLK).
Max 104 MHz Transmit Clock for level-3 operation. All transmit signals
are sampled on rising edge of the clock.
POS:
Transmit Error Indicator (TERR) signal.
TERR is used to indicate that the current packet should be aborted.
When TERR is set HIGH, the current packet is aborted. TERR should
only be asserted when TEOP is asserted.
HBST:
Transmit Error Indicator (TERR) signal.
A HIGH indicates the current packet or cell has error.
POS:
Transmit Write Enable (TENB) signal.
The TENB signal is used to control the flow of data to the transmit
FIFOs. When TENB is HIGH, the TDAT, TMOD, TSOP, TEOP, and
TERR signals are invalid and are ignored by POSIC2GVC. The TSX
signal is valid and is processed by POSIC2GVC when TENB is HIGH.
When TENB is LOW, the TDAT, TMOD, TSOP, TEOP and TERR
signals are valid and are processed by POSIC2GVC. Also, the TSX
signal is ignored by POSIC2GVC when TENB is LOW.
ATM:
Transmit write enable (TxEnb*).
This signal is an active LOW input which is used to initiate writes to
the transmit FIFOs.
When TxEnb* is sampled HIGH, the information sampled on the
TxData, TxPrty, and TxSOC signals are invalid. When TxEnb* is
sampled LOW, the information sampled on the TxData, TxPrty, and
TxSOC signals are valid and are written into the transmit FIFO.
TxEnb* is sampled on the rising edge of TxClk.
HBST:
Transmit Data Valid (TDVAL_n) signal.
The TDVAL_n signal is used to control the flow of data to the transmit
FIFOs. When TDVAL_n is HIGH, the TDATA, TBVAL, TSOP, TADDR,
TSOP, TEOP, and TERR signals are valid and are processed by
POSIC2GVC.
Pin Description
CY7C9536B
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