CY7C9536B-BLC Cypress Semiconductor Corp, CY7C9536B-BLC Datasheet

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... Applications • Multi-service nodes • ATM switches and routers • Packet routers and multiservice routers • SONET/SDH/Add-Drop Mux for packet/data applications • SONET/SDH/ATM/POS test equipment • 3901 North First Street CY7C9536B [14,15] , • San Jose CA 95134 • 408-943-2600 Revised April 25, 2005 ...

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... CpuTs_n/ TDAT[31:0] CapuAds_n TPRTY CpuSel TADD[3:0] CpuBlast_n TMOD[1:0] CpuTa_n TSOP ChipSel TEOP CpuInt STPA CpuClkFail PTCA CpuWrRd TENB CpuAD[31:0] TSX Mode DTCA[3:0] CY7C9536B RXD[31:0] RXCLK RXCLKs SONETRX_PARIN LFI RX SONET Line Interface Clk16MHz Receive SONET Receiv De-Framer Clk2MHz e SONE Receive SONET POHSDOUT T ...

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... Overview The CY7C9536B (POSIC2GVC highly integrated SONET/SDH framer device for transport of ATM and IP packets over SONET/SDH links. It features special functions and architecture to support next-generation optical networking protocols for both SONET/SDH and direct data-over-fiber networks. OIF-SPI (POS-PHY) level 3, UTOPIA level 3 and High-Bandwidth Synchronous Transfer (HBST) interfaces are provided on the system side ...

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... VC-3-4v/STS-1-4v VC-3-5v/STS-1-5v VC-3-6v/STS-1-6v VC-3-7v/STS-1-7v VC-3-8v/STS-1-8v VC-4-1v/STS-3c-1v VC-4-2v/STS-3c-2v VC-4-3v/STS-3c-3v VC-4-4v/STS-3c-4v VC-4-5v/STS-3c-5v VC-4-6v/STS-3c-6v VC-4-7v/STS-3c-7v VC-4-8v/STS-3c-8v VC-4-4c-1v/STS-12c-1v VC-4-4c-2v/STS-12c-2v VC4-8c-1v/STS-24c-1v CY7C9536B [16] [17] (~50 Mbps) (~100 Mbps) (~150 Mbps) (~200 Mbps) (~250 Mbps) (~300 Mbps) (~350 Mbps) (~400 Mbps) [17] (~150 Mbps) (~300 Mbps) (~450 Mbps) (~600 Mbps) ...

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... In the transmit direction, it computes a 16-bit header CRC based on 2-byte length value received from the link layer device. The length and CRC fields are inserted as header of the frame ahead of the packet. Scrambling of the payload and 32-bit payload CRC computation and insertion are optional. CY7C9536B 1Gb CH Packet 1 ...

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... OIF-SPI level 3. ATM cells can also be transferred over OIF-SPI level 3 bus. System interface can be programmed in HBST mode. In this case, a separate set of address pins are supported on the system side. This mode supports high-speed burst access. CY7C9536B Frame SPI-3/ Tagger UTOPIA ...

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... MHz 32 bits 77.76 MHz Clock Source The transmit clock can be programmed to be one of the following sources: • Received clock supplied by the PHY • External transmit clock source. CY7C9536B Data SONET/SDH Clock Frequency Line Rate OC-3/STM-1 OC-12/STM-4 OC-12/STM-4 OC-48/STM-16 OC-48/STM-16 ...

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... APS ports (per linear 1+1 APS requirements). When protection switching, POSIC2GVC can be programmed to switch line inputs from the main receive port to the APS receive port, or vice versa. This APS scheme provides solely optical/PHY link level protection. CY7C9536B RxS RxM POSIC STANDBY TxS RxS ...

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... Document #: 38-02078 Rev. *G CONFIDENTIAL OSC Main OC-48 PHY REFCLK TXCLKI TXCLKO M TXCLKO TXCLKI TXD[15:0] TXD [15:0] RXD[15:0] RXD[15:0] RXCLK RXCLK LFI LFI M Standby PHY REFCLK TXCLKO LFI TXCLKI TXD [15:0] RXD[15:0] RXCLKS RXCLK CY7C9536B SFF Optical Module SFF Optical Module Page ...

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... Pin Configuration Document #: 38-02078 Rev. *G CONFIDENTIAL CY7C9536B (POSIC2GVC) Bottom View POSIC TM (CY7C9536) Pin Diagram Bottom View CY7C9536B Page ...

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... Receive POH Serial Port Data Start Indication. Active HIGH pulse generated once in every 125 ms. Indicates that the POSIC2GVC expects the first bit of the first byte of RPOH should accompany the next clock edge Transport over head serial port data output. CY7C9536B Pin Description Page ...

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... LINK Layer device and the POSIC2GVC. RFCLK may cycle at a rate up to 100 MHz. ATM: Transfer/interface clock (RxClk) HBST: Receive Clock (RCLK). Max 104 MHz Receive Clock for level-3 operation. All signals are latched out on the rising edge of this clock. CY7C9536B Pin Description Page ...

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... ATM: Receive Parity (RxPrty) signal. Data bus odd parity. HBST: Receive bus parity (RPARITY) signal. Receive bus parity, Even/Odd parity calculated on the data bus alone or on all the bus signals (RDATA, RADDR, RDVAL, RBVAL, RSOP, REOP, RERR). CY7C9536B Pin Description Page ...

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... RSX indicates when the in-band port address is present on the RDAT bus. When RSX is HIGH and RVAL is LOW, the value of RDAT[7:0] is the address of the receive FIFO to be selected by POSIC2GVC. Subsequent data transfers on the RDAT bus will be from the port as specified by the in band address. CY7C9536B Pin Description Page ...

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... TxEnb* is sampled on the rising edge of TxClk. HBST: Transmit Data Valid (TDVAL_n) signal. The TDVAL_n signal is used to control the flow of data to the transmit FIFOs. When TDVAL_n is HIGH, the TDATA, TBVAL, TSOP, TADDR, TSOP, TEOP, and TERR signals are valid and are processed by POSIC2GVC. CY7C9536B Pin Description Page ...

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... Address 31 indicates a null port. ATM: Transmit address bus (TxAddr) bus. Address of POSIC2GVC channel being selected. HBST: Port Address (TADDR) bus. Address driven by the Link Layer to indicate the port address of current data transfer. CY7C9536B Pin Description Page ...

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... CPU programmable registers. DTPA is updated on the rising edge of TFCLK. HBST: Polled FIFO available Status (TFAST) bus. When the signal TSOFST is active, the status of channels 0,4,8,12 is given first followed by 1,5,9,13 and 2,6,10,14 and the last 3,7,11,15. CY7C9536B Pin Description Page ...

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... TFAST bus. This signal is repeated once in every four clocks POS: Transmit Start of Transfer (TSX) signal. TSX indicates inband port address on the TDAT bus. When TENB is HIGH and TSX is asserted (HIGH), the value of TADR[3:0] is the address of transmit FIFO selected. TSX is valid only when TENB is deasserted. CY7C9536B Pin Description Page ...

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... CPU Clock Used to select between Intel and Motorola CPU. ‘0’ = Motorola, ‘1’ = Intel 1 Y Transfer Start. Active LOW 1 Y Write/Read Signal. In Intel mode, active HIGH for write operation. In Motorola mode, active LOW for write operation. CY7C9536B Pin Description Page ...

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... The POSIC2GVC Output Enable (POSIC_OEN) signal. When set to logic one, all POSIC2GVC outputs (except CpuTa_n and CLKOUT) are held three-state. When POSIC_OEN is set to logic zero, all inter- faces are enabled. Pull-down to ‘0’ for normal operation. 336 85 83 504 I/Os: 336; Power: 168 CY7C9536B Pin Description Page ...

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... CY7C9536B Pin Type LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT ...

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... AB6 AC2 AC3 AC4 AC5 AC6 AD2 AD4 V4 AD5 AE2 AF5 AE6 AG5 AF6 AD7 AG6 CY7C9536B Pin Type LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN ...

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... AF15 AG15 AH15 AE16 AF16 AH16 AE17 AF10 AF18 AG18 AG10 AH10 AE11 AF11 AG11 AH11 AG16 AE18 AJ17 CY7C9536B Pin Type LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT Open Drain Output LVTTL_OUT LVTTL_OUT LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO ...

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... AG25 AE26 AG26 AE27 AD25 AD28 AD27 AB26 AB25 AB24 AA28 AA27 AA26 AA25 AA24 Y29 Y28 AD26 Y27 W27 CY7C9536B Pin Type LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_IN LVTTL_OUT LVTTL_OUT LVTTL_OUT ...

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... K29 L25 L26 L27 L28 M26 M27 M28 N25 N26 J24 N27 N29 P25 P27 P28 R25 R26 R28 T25 CY7C9536B Pin Type HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTL_OUT HSTL/LVTTLLVPECL_IN 0 ...

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... E21 D21 C21 B21 E20 C20 B20 E19 B19 F26 B18 A18 E26 F25 D25 C25 G24 E24 B17 D19 CY7C9536B Pin Type HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN HSTL/LVTTL/LVPECL_IN LVTTL_IN HSTL/LVTTL/LVPECL_IN LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO ...

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... E15 D15 E14 C14 B14 E13 E12 E11 D11 E10 CY7C9536B Pin Type LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_OUT LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO ...

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... C1, E1, F1, H1, K1, R1, Y1, AB1, A3, H3, A5, AJ6, A8, D8, AJ8, AJ10, D14, A15, B15, AJ15, E18, A19, AJ20, E23, A24, AJ24, G25, AJ25, B26, C27, AG27, B28, AG29 AE25, AG28, T29, V29, AA29, AB29, AD29, Y26 CY7C9536B Pin Type LVTTL_IO LVTTL_IO LVTTL_IO LVTTL_IO ...

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... Consult factory for Power Consumption with external termination resistors. Document #: 38-02078 Rev. *G CONFIDENTIAL Parameter V CC1 0°C to +70°C 1.71V to 1.89V 1.71V to 1.89V Test Conditions 20-pF capacitive load 20-pF capacitive load 20-pF capacitive load 20-pF capacitive load CY7C9536B Value – 150 125 220 2.43 4.785 4.785 4.785 ...

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... 1.71V CC1 V = 1.89V CC1 All V = Max CC1 All V = Max All V = Max CC2 All V = Max CY7C9536B Min. Max. Unit –20 –100 mA 2.4 – 0 0.3 V CC2 –0.3 0.8 V µA – 10 µA – –10 0.68 0.9 V – 0.4 – V CC5 – ...

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... Document #: 38-02078 Rev. *G CONFIDENTIAL 2.0V Output V = 1.4V th 0.8V < 1ns 80% Output V = 0.75V th 20% < 1ns R1 80 2.0V th Output 20% < 1ns (c) LVPECL-compliant Termination CY7C9536B 1. ohm T-line R1=125 ohm Test Point C < 20pF (a) LVTTL AC Test Load 1. ohm Test R1=100 ohm T-line Point R2=100 ohm < ...

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... Table 6 details the timing requirements. Compatible/Suggested Part Number CYS25G0101DX CY7C1370B/C or CY7C1464V33 (min. 200-MHz grade) Compatible with Intel/Motorola CPUs Description CY7C9536B , V , and V in this case. CC1 CC2 CC3 , and V if HSTL I/O is not used. CC1 ...

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... CONFIDENTIAL Description Description [23] [24] [23] [24] [23] [24] [23] [24] [23] [24] [23] [24] [23] [24] [23] [24] [23] [24] [25, 26] [25, 26] [25, 26] Description [23] [24] [25, 26] [25, 26] CY7C9536B Min. Max. Unit – 1.5 ns 1.5 – ns 1.25 – ns 1.5 – ns 1.25 – ns 1.5 – ns 1.25 – ns Min. Max. Unit 104 ...

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... TPARITY Hold Time to TCLK TPARITYH t TBVAL[2:0] Set-up Time to TCLK TBVALS t TBVAL[2:0] Hold Time to TCLK TBVALH t TDVAL_n Set-up Time to TCLK TDVALS Document #: 38-02078 Rev. *G CONFIDENTIAL Description [25, 26] [25, 26] [25, 26] [25, 26] [25, 26] Description Description Description CY7C9536B Min. Max. Unit Min. Max. Unit – ...

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... ADV/LD Output Delay after CLKOUT Rise ADVO t ADV/LD Output Hold after CLKOUT Rise ADVOH t DQ Input Set-up before CLKOUT Rise Input Hold after CLKOUT Rise DH Document #: 38-02078 Rev. *G CONFIDENTIAL Description Description Description CY7C9536B Min. Max. Unit 0.5 – – ns 0.5 – – ns 0.5 – ...

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... Clk16MHz Fall Time Clk16MHzF [22] t RPOHSTART Pulse Width RPOHPW t RPOHSTART Output Delay after Clk16MHZ Rising Edge RPOHO t POHSDOUT Output Delay after Clk16MHZ Rising Edge POHSDOUTO Document #: 38-02078 Rev. *G CONFIDENTIAL Description Description Description CY7C9536B Min. Max. Unit [27] 133 133.33 MHz – 66 MHz 7 – – ...

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... Set-up Time of POHSDIN before Falling Edge of Clk16MHz POHSDINS t Hold Time of POHSDIN after Falling Edge of Clk16MHz POHSDINH Note: 27. All VC mode configurations require a SYSCLK frequency of 133.33 MHz. Document #: 38-02078 Rev. *G CONFIDENTIAL Description Description CY7C9536B Min. Max. Unit 31 34 SYSCLK cycles 31 34 SYSCLK cycles – ...

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... Switching Waveforms Line Transmit and Receive Interface Timing t RXCLKH RXCLK RXD[31:0] RXFRAME_PULSE SONETRX_PARIN t TXCLKR TXCLKOUT TXD[31:0] TXFRAME_PULSE SONETTX_PAROUT TXCLKI Document #: 38-02078 Rev. *G CONFIDENTIAL t RXCLKP t RXCLKL t RXDH t RXDS t RXFPS t PARINS t TXCLKF t TXDO t TXCLKP t TXFPO t TXFPPW t PAROUTO t TXCLKIP CY7C9536B t RXFPH t PARINH Page ...

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... PTADR[3:0] TMOD[1:0] DTPA[3:0] STPA PTCA Document #: 38-02078 Rev. *G CONFIDENTIAL t t TENBS TENBH t t TDATH TDATS t t TPRTYH TPRTYS t t TSOPS TSOPH t t TEOPS TEOPH t t TERRH TERRS t t TSXH TSXS t t PTADRH PTADRS t t TMODS TMODH t DTPAO t STPAO t PTCAO CY7C9536B Page ...

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... Transmit UTOPIA Level 3 System Interface Timing TxClk TxEnb TxAddr[4:0] TxData[31:0] TxPrty TxSoc PTCA Document #: 38-02078 Rev. *G CONFIDENTIAL t t RENBS RENBH t RDATO t RPRTYO t RSOPO t REOPO t RERRO t RVALO t RMODO t RSXO t t TxEnbS TxEnbH t t TxAddrS TxAddrH t t TxDataS TxDataH t t TxPrtyS TxPrtySH t t TxSocS TxSocH t PTCAO CY7C9536B Page ...

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... TFAST[3:0] Document #: 38-02078 Rev. *G CONFIDENTIAL t t RxEnbH RxEnbS t RxDataO t RxPrtyO t RxSocO t RxClavO t t TADDRH TADDRS t t TDATAS TDATAH t t TBVALS TBVALH t t TDVALS TDVALH t t TSOPH TSOPS t t TEOPS TEOPH t t TERRS TERRH t t TPARITYS TPARITYH CY7C9536B t TSTFAO t TSOFSTO t TFASTO Page ...

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... CH CLKOUT CEN t CENOH t ADOH AD[18:0] DQ1[31:0] & DQ2[31: WEOH ADV/LD t ADVOH Document #: 38-02078 Rev. *G CONFIDENTIAL t RREADYS t CLKOUTO t CYC CENO t ADO t CLZ Data WEO t ADVO CY7C9536B t RREADYH t RADDRO t RDATAO t RBVALO t RDVALO t RSOPO t REOPO t RERRO t RSTFAO t RPARITYO t DOH Data Out t CHZ Page ...

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... Switching Waveforms (continued) CPU System Interface Timing CpuClk CpuTs_n / CpuAds_n CpuAD[31:0] (Input) CpuAD[31:0] (Output) CpuWrRd CpuTa_n CpuBlast_n / CpuBdip_n ChipSel CpuInt Document #: 38-02078 Rev. *G CONFIDENTIAL t CpuAdsH t CpuAdsS t CpuADS t CpuADO t CpuWrRdH t CpuWrRdS t CpuTaO t CpuBlastS t CpuSelS t CpuIntO CY7C9536B t CpuADZ t CpuADH t CpuBlastH t CpuSelH Page ...

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... TE2 STROBE TOHSDIN POH Serial Interface Timing Clk16MHz RPOHSTART POHSDOUT TPOHSTART POHSDIN Document #: 38-02078 Rev. *G CONFIDENTIAL t Clk2MHzR t REPW t REO t TEPW t TEO t TOHDINS t Clk16MHzR t RPOHO t TPOHO t POHSDINS CY7C9536B t Clk2MHzP t Clk2MHzF t REO t TOHSDOUTO t TEO t TOHDINH t Clk16MHzP t Clk16MHzF t RPOHPW t RPOHSDOUTO t RPOHO t TPOHPW t TPOHO t POHSDINH Page ...

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... Ordering Information Speed Ordering Code Standard CY7C9536B-BLC Standard CY7C9536B-BLI Package Diagram 504-Lead L2 Ball Grid Array (37.50 x 37.50 x 1.57 mm) BL504 Please see Device Manual and errata document for further details on functional descriptions. POSIC2GVC and NoBL are trade- marks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders ...

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... Document History Page Document Title:CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC™ Document Number: 38-02078 Orig. of REV. ECN No. Issue Date Change ** 127207 07/03/03 *A 129314 10/17/03 *B 130893 12/24/03 *C 132897 01/26/04 *D 207426 See ECN *E 215296 See ECN *F 318033 See ECN *G 355154 See ECN Document #: 38-02078 Rev. *G ...