LH28F008SAT-12 Sharp Electronics, LH28F008SAT-12 Datasheet - Page 8

• Manufacturer Part Number: LH28F008SAT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAT-12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

LH28F008SA
command to the Command User Interface (array, intel-
ligent identifier, or Status Register). The LH28F008SA
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown. The
LH28F008SA has four control pins, two of which must
be logically active to obtain data at the outputs. Chip
Enable (CE
active enables the selected memory device. Output
Enable (OE
direction control, and when active drives data from the
selected memory onto the I/O bus. PWD and WE
also be at V
forms.
Output Disable
puts are disabled. Output pins (DQ
in a high-impedance state.
Standby
in standby mode. Standby operation disables much of
the LH28F008SA’s circuitry and substantially reduces
device power consumption. The outputs (DQ
are placed in a high-impedance state independent of
Command Definitions
NOTES:
1. Bus operations are defined in Bus Operations Table.
2. IA = Identifier Address: D0H for manufacturer code, 01H for device code.
3. SRD = Data read from Status Register. See Status Register Definitions Table for a description of the Status Register bits.
4. Following the intelligent identifier command, two read operations access manufacture and device codes.
5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
6. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
8
Read Array/Reset
Intelligent Identifier
Read Status Register
Clear Status Register
Erase Setup/Erase Confirm
Erase Suspend/Erase Resume
Byte Write Setup/Write
Alternate Byte Write Setup/Write
The first task is to write the appropriate read mode
With OE
CE
BA = Address within the block being erased.
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched on the rising edge of WE
IID = Data read from intelligent identifiers.
»
at a logic-high level (V
COMMAND
»
»
IH
) is the device selection control, and when
at a logic-high level (V
»
) is the data input/output (DQ
. Figure 8 illustrates read bus cycle wave-
IH
) places the LH28F008SA
CYCLES
0
REQ'D
IH
BUS
- DQ
), the device out-
1
3
2
1
2
2
2
2
7
) are placed
0
OPER.
0
Write
Write
Write
Write
Write
Write
Write
Write
- DQ
- DQ
»
must
FIRST BUS CYCLE
7
7
)
)
ADDRESS
WA
WA
BA
X
X
X
X
X
the status of OE
ing block erase or byte write, the device will continue
functioning and consuming normal active power until
the operation completes.
Deep Power-Down
entered when PWD is at V
is 0.20 µA typical in deep powerdown mode, with cur-
rent draw through V
modes, PWD-low deselects the memory, places output
drivers in a high-impedence state and turns off all inter-
nal circuits. The LH28F008SA requires time t
AC Characteristics-Read-Only Operations) after return
from powerdown until initial memory access outputs are
valid. After this wakeup interval, normal operation is re-
stored. The Command User interface is reset to Read
Array, and the upper 5 bits of the Status Register are
cleared to value 100,000, upon return to normal opera-
tion.
will abort either operation. Memory contents of the block
being altered are no longer valid as the data will be par-
tially written or erased. Time t
logic-high (V
be written.
The LH28F008SA offers a deep power-down feature,
During block erase or byte write modes, PWD low
DATA
FFH
90H
70H
50H
20H
B0H
40H
10H
»
.
IH
) is required before another command can
»
. If the LH28F008SA is deselected dur-
OPER.
Read
Read
Write
Write
Write
Write
SECOND BUS CYCLE
PP
typically 0.1 µA. During read
ADDRESS
IL
8M (1M × 8) Flash Memory
. Current draw through V
WD
WD
BA
IA
PHWL
X
X
after PWD goes to
DATA
SRD
D0H
D0H
WD
WD
IID
PHQV
2, 3, 4
2, 3, 5
2, 3, 5
NOTE
1
3
2
(see
CC