LH28F008SAT-12 Sharp Electronics, LH28F008SAT-12 Datasheet - Page 11

• Manufacturer Part Number: LH28F008SAT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAT-12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

8M (1M × 8) Flash Memory
to the Command User Interface to read data from blocks
other than that which is suspended. The only other valid
commands at this time are Read Status Register (70H)
and Erase Resume (D0H), at which time the WSM will
continue with the erase process. The Erase Suspend
Status and WSM Status bits of the Status Register will
be automatically cleared and RY
After the Erase Resume command is written to it, the
LH28F008SA automatically outputs Status Register data
when
Flowchart). V
LH28F008SA is in Erase Suspend.
Byte Write Setup/Write Commands
The Byte Write Setup command (40H) is written to the
Command User Interface, followed by a second write
specifying the address and data (latched on the rising
edge of WE
controlling the byte write and write verify algorithms
internally. After the two-command byte write sequence
is written to it, the LH28F008SA automatically outputs
Status Register data when read (see Byte Write Flow-
chart). The CPU can detect the completion of the byte
write event by analyzing the output of the RY
the WSM Status bit of the Status Register. Only the Read
Status Register command is valid while byte write is
active.
bit should be checked. If byte write error is detected,
the Status Register should be cleared. The internal
WSM verify only detects errors for '1's that do not suc-
cessfully write to '0's. The Command User Interface re-
mains in Read Status Register mode until further
commands are issued to it. If byte write is attempted
while V
Byte write attempts while V
spurious results and should not be attempted.
EXTENDED BLOCK ERASE/BYTE
WRITE CYCLING
block erase cycles on each of the sixteen 64K blocks.
Low electric fields, advanced oxides and minimal oxide
area per cell subjected to the tunneling electric field
combine to greatly reduce oxide stress and the prob-
ability of failure. A 20M solid-state drive using an array
of LH28F008SAs has a MTBF (Mean Time Between
Failure) of 33.3 million hours(1), over 600 times more
reliable than equivalent rotating disk technology.
At this point, a Read Array command can be written
Byte write is executed by a two-command sequence.
When byte write is complete, the Byte Write Status
The LH28F008SA is designed for 100,000 byte write/
PP
read
= V
»
) to be written. The WSM then takes over,
PPL
PP
(see
, the V
must remain at V
PP
Erase
Status bit will be set to '1'.
PPL
< V
»
/ BY
Suspend/Resume
PP
»
will return to V
< V
PPH
PPH
»
/ BY
while the
produce
»
pin, or
OL
.
AUTOMATED BYTE WRITE
gramming algorithm using the Command User Interface,
Status Register and Write State Machine (WSM).
On-chip integration dramatically simplifies system soft-
ware and provides processor interface timings to the
Command User Interface and Status Register. WSM
operation, internal verify and V
are monitored and reported via the RY
appropriate Status Register bits. Figure 5 shows a sys-
tem software flowchart for device byte write. The entire
sequence is performed with V
or V
data is partially written at the location where byte write
aborted. Block erasure, or a repeat of byte write, is re-
quired to initialize this data to a known value.
AUTOMATED BLOCK ERASE
mented internally, including all preconditioning of block
data. WSM operation, erase success and V
age presence are monitored and reported through
RY
mand other than Erase Confirm is written to the device
following Erase Setup, both the Erase Status and Byte
Write Status bits will be set to '1's. When issuing the
Erase Setup and Erase Confirm commands, they should
be written to an address within the address range of the
block to be erased. Figure 6 shows a system software
flowchart for block erase.
The Erase Suspend/Erase Resume command
sequence allows suspension of this erase operation to
read data from a block other than that in which erase is
being performed. A system software flowchart is shown
in Figure 7.
Abort occurs when PWD transitions to V
to V
tially erased by this operation, and a repeat of erase is
required to obtain a fully erased block.
The LH28F008SA integrates the Quick-Pulse pro-
Byte write abort occurs when PWD transitions to V
As above, the Quick-Erase algorithm is now imple-
Erase typically takes 1.6 seconds per block.
The entire sequence is performed with V
»
/ BY
PP
PPL
drops to V
»
, while erase is in progress. Block data is par-
and the Status Register. Additionally, if a com-
PPL
. Although the WSM is halted, byte
PP
PP
high voltage presence
at V
PPH
»
/ BY
LH28F008SA
.
IL
PP
»
or V
PP
output and
high volt-
at V
PP
PPH
fails
11
IL
,
.