LH28F008SAT-12 Sharp Electronics, LH28F008SAT-12 Datasheet - Page 10

• Manufacturer Part Number: LH28F008SAT-12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SAT-12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

LH28F008SA
Read Array Command
powerdown mode, the LH28F008SA defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microprocessor
read cycles retrieve array data. The device remains en-
abled for reads until the Command User Interface con-
tents are altered. Once the internal Write State Machine
has started a block erase or byte write operation, the
device will not recognize the Read Array command, until
the WSM has completed its operation. The Read Array
command is functional when V
Intelligent Identifier Command
operation, initiated by writing 90H into the Command
User Interface. Following the command write, a read
cycle from address 00000H retrieves the manufacturer
code of 89H. A read cycle from address 00001H
returns the device code of A2H. To terminate the opera-
tion, it is necessary to write another valid command into
the register. Like the Read Array command, the intelli-
gent identifier command is functional when V
or V
Read Status Register Command
may be read to determine when a byte write or block
erase operation is complete, and whether that opera-
tion completed successfully. The Status Register may
be read at any time by writing the Read Status Register
command (70H) to the Command User Interface. After
writing this command, all subsequent read operations
output data from the Status Register, until another valid
command is written to the Command User Interface.
The contents of the Status Register are latched on the
falling edge of OE
read cycle. OE
further reads to update the Status Register latch.
The Read Status Register command functions when
V
Clear Status Register Command
to '1's by the Write State Machine and can only be reset
by the Clear Status Register Command. These bits
indicate various failure conditions (see Status Register
Definitions). By allowing system software to control the
resetting of these bits, several operations may be per-
formed (such as cumulatively writing several bytes or
erasing multiple blocks in sequence). The Status Reg-
ister may then be polled to determine if an error
occurred during that sequence. This adds flexibility to
the way the device may be used.
10
PP
Upon initial device powerup and after exit from deep
The LH28F008SA contains an intelligent identifier
The LH28F008SA contains a Status Register which
The Erase Status and Byte Write Status bits are set
PPH
= V
.
PPL
or V
»
PPH
or CE
»
or CE
.
»
must to toggled to V
»
, whichever occurs last in the
PP
= V
PPL
or V
PP
PPH
IH
= V
before
.
PPL
set by system software before further byte writes or block
erases are attempted. To clear the Status Register, the
Clear Status Register command (50H) is written to the
Command User Interface. The Clear Status Register
command is functional when V
Erase Setup/Erase Confirm Commands
two-cycle command sequence. An Erase Setup com-
mand (20H) is first written to the Command User Inter-
face, followed by the Erase Confirm command (D0H).
These commands require both appropriate sequenc-
ing and an address within the block to be erased to FFH.
Block preconditioning, erase and verify are all handled
internally by the Write State Machine, invisible to the
system. After the two-command erase sequence is writ-
ten to it, the LH28F008SA automatically outputs Status
Register data when read (see Block Erase Flowchart).
The CPU can detect the completion of the erase event
by analyzing the output of the RY
Status bit of the Status Register.
be checked. If erase error is detected, the Status Reg-
ister should be cleared. The Command User Interface
remains in Read Status Register mode until further com-
mands are issued to it.
execution insures that memory contents are not
accidentially erased. Also, reliable block erasure can only
occur when V
voltage, memory contents are protected against era-
sure. If block erase is attempted while V
V
V
not be attempted.
Erase Suspend/Erase Resume Commands
interruption in order to read data from another block of
memory. Once the erase process starts, writing the
Erase Suspend command (B0H) to the Command User
Interface requests that the WSM suspend the erase
sequence at a predetermined point in the erase algo-
rithm. The LH28F008SA continues to output Status
Register data when read, after the Erase Suspend com-
mand is written to it. Polling the WSM Status and Erase
Suspend Status bits will determined when the erase
operation has been suspended (both will be set to '1').
RY
PPL
PP
Additionally, the V
Erase is executed one block at a time, initiated by a
When erase is completed, the Erase Status bit should
This two-step sequence of set-up followed by
The Erase Suspend command allows block erase
»
/ BY
Status bit will be set to '1'. Erase attempts while
< V
»
will also transition to V
PP
< V
PP
PPH
= V
produce spurious results and should
PP
PPH
Status bit (SR.3) MUST be re-
. In the absence of this high
8M (1M × 8) Flash Memory
OH
PP
.
»
/ BY
= V
PPL
»
pin, or the WSM
PP
or V
= V
PPH
PPL
.
, the