NOII4SM6600A-QDC ON Semiconductor, NOII4SM6600A-QDC Datasheet - Page 9

• Manufacturer Part Number: NOII4SM6600A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII4SM6600A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

The complete output amplifier can be put in standby by setting the corresponding bit in the AMPLIFIER register.
Stage 1: Offset, FPN Correction, and Multiplexing
In the first stage, the signals from the buses are subtracted and
the offset from the DACs is added. After a system reset, the
analog multiplexer is configured for two outputs (see the bit
settings in the
ONE_OUT is set to 1, the two signals S1 and S2 are multiplexed
to one output (output 1). The amplifiers of Stage 2 and Stage 3
of the second output path are then put in standby. The speed and
power consumption of the first stage can be controlled through
the resistor connected to CMD_OUT_1.
Stage 2: Programmable Gain Amplifier
The second stage provides the gain, which is adjustable
between 1.36 and 17.38 in steps of approximately 20.25 (~1.2).
An overview of the gain settings is given in
and power consumption of the second stage can be controlled
through the resistor connected to CMD_OUT_2.
Table 5. PGA Gain Settings
0000
0001
Bits
AMPLIFIER Register
DC Gain
bus1_R
bus2_R
bus1 S
bus2 S
1.36
1.64
DAC_raw /
DAC_dark
DAC_fine
+
+
1000
1001
Bits
A2
A1
on page 22). In case
Table
Figure 7. Output Amplifier Architecture
S2
S1
Rev. 9 | www.onsemi.com | Page 9 of 32
DC Gain
5. The speed
5.40
6.35
multiplexer
Stage 1
analog
Table 5. PGA Gain Settings
Stage 3: Output Drivers
The speed and power consumption of the third stage can be
controlled through the resistor connected to CMD_OUT_3. The
output drivers are designed to drive a 20 pF output load at
40 Msamples/s with a bias resistor of 100 k.
Offset DACs
Figure 8
reference voltages of the two different channels. The offset is
mainly given through DAC_raw. DAC_fine can be used to shift
the reference voltage of bus 2 up or down to compensate for
different offsets in the two channels.
programmable
gain amplifiers
0010
0011
0100
0101
0110
Stage 2
0111
Bits
shows how the DAC registers influence the black
DC Gain
1.95
2.35
2.82
3.32
3.93
4.63
drivers
output
Stage 3
1
1
Pixel output 2
Pixel output
1010
1011
1100
1101
1110
1111
Bits
NOII4SM6600A
DC Gain
10.31
12.36
14.67
17.38
7.44
8.79