NOII4SM6600A-QDC ON Semiconductor, NOII4SM6600A-QDC Datasheet - Page 28

• Manufacturer Part Number: NOII4SM6600A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII4SM6600A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 16. Pin List (continued)
Note on Power On Behavior
At power on, the chip is in an undefined state. It is advised that the power on is accompanied by the assertion of the SYS_CLOCK
and a SYS_RESET pulse that puts all internal registers in their default state (all bits are set to 0). The X-shift registers are in a defined
state after the first X_SYNC, which occurs a few microseconds after the first Y_START and Y_CLOCK pulse. Before this X_SYNC,
the chip may draw more current from the analog power supply V
supplies. The current spike (if there are any) may also be avoided by a slower ramp up of the analog power supply or by disconnecting
the resistor on pin 3 (CMD_COLAMP) at startup.
Package Outline Drawing
63
64
65
66
67
68
Pin
ADC_D<0>
BS_RESET
BS_CLOCK
BS_DIN
BS_BUS
CMD_DEC
Pin Name
Pin Type
Output
Output
Input
Input
Input
Input
Figure 23. 68 Pin LCC Packaging Outline
-
-
-
-
-
0.74
Expected Voltage [V]
Rev. 9 | www.onsemi.com | Page 28 of 32
DDA
. It is therefore favorable to have separate analog and digital
ADC data output (LSB)
Boundary scan (allows debugging of internal nodes): Reset.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): Clock.
Tie to GND if not used.
Boundary scan (allows debugging of internal nodes): In. Tie
to GND if not used.
Boundary scan (allows debugging of internal nodes): Bus.
Leave floating if not used.
Biasing of X and Y decoder. Connect to V
and decouple to GNDD with C = 100 nF.
Pin Description
NOII4SM6600A
DDD
with R = 50 k