NOII4SM6600A-QDC ON Semiconductor, NOII4SM6600A-QDC Datasheet - Page 23

• Manufacturer Part Number: NOII4SM6600A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII4SM6600A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Timing Diagrams
Sequencer Control Signals
There are 3 control signals that operate the image sensor:
■
■
■
Basic Frame and Line Timing
The basic frame and line timing of the IBIS4-6600 sensor is shown in
The pulse width of Y_CLOCK must be a minimum of one clock cycle and three clock cycles for Y_START. As long as Y_CLOCK is
applied, the sequencer stays in a suspended state.
Both EOF and EOL can be tied to Y_START (EOF) and Y_CLOCK (EOL) if both signals are delayed with at least 2 SYS_CLOCK
periods to let the sensor run automatically. It must however be noted that on power-on, the FIRST Y_START and Y_CLOCK must be
generated by the external system.
T1
T2
T3
T4
SYS_CLOCK
Y_CLOCK
Y_START
Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel
reset levels, and start the readout of one line. It depends on the granularity of the X-sequencer clock (see
Pixels counted by pixel counter until the value of Nrof_pixels register is reached. Pixel_valid goes high when the internal
X_sync signal is generated. In other words, when the readout of the pixels is started. Pixel_valid goes low when the pixel
counter reaches the value loaded in the Nrof_pixels register. Eol goes high Sys_clock cycle after the falling edge of Pixel_valid.
EOF goes high when the line counter reaches the value loaded in the NROF_LINES register and the line is read (PIXEL_VALID
goes low).
The time delay between successive Y_CLOCK pulses needs to be equal to avoid any horizontal illumination (integration)
discrepancies in the image.
Figure 17. Relative Timing of the Three Control Signals
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These control signals must be generated by the external system
with the following time constraints to SYS_CLOCK
(rising edge = active edge):
■
■
It is important that these signals are free of any glitches.
Figure
TSETUP >7.5 ns
THOLD > 7.5 ns
18.
NOII4SM6600A
Table 13
on page 20).