NOII4SM6600A-QDC ON Semiconductor, NOII4SM6600A-QDC Datasheet - Page 25

• Manufacturer Part Number: NOII4SM6600A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII4SM6600A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

ADC Timing
Two Analog Outputs
Figure 21
(in case of internal clock, the clock is half the SYS_CLOCK).
T1: Each ADC has a pipeline delay of 2 ADC_CLOCK cycles. This results in a total pipeline delay of four pixels.
One Analog Output
Figure 22
T1: The ADC has a pipeline delay of 2 ADC_CLOCK cycles.
shows the timing of the ADC using two analog outputs. Internally, the ADCs sample on the falling edge of the ADC_CLOCK
shows the timing of the ADC using one analog output. Internally, the ADC samples on the falling edge of the ADC_CLOCK.
Figure 20. Pixel Output Timing Multiplexing to One Analog Output
Figure 21. ADC Timing using Two Analog Outputs
Figure 22. ADC Timing using One Analog Output
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NOII4SM6600A