NOIS1SM0250A-HHC ON Semiconductor, NOIS1SM0250A-HHC Datasheet - Page 16

• Manufacturer Part Number: NOIS1SM0250A-HHC
• Manufacturer: ON Semiconductor

Specifications of NOIS1SM0250A-HHC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 10. Digital Input Signals (continued)
Table 11. Digital Output Signals
Pin
Pin
13
14
15
16
17
18
19
20
21
22
24
25
27
28
36
37
38
71
75
80
23
26
29
55
56
57
6
7
8
BITINVERT
SYNC_YR
Pin Name
SYNC_YL
CLK_ADC
Pin Name
TRI_ADC
EOS_YR
SYNC_X
CLK_YR
EOS_YL
CLK_YL
EOS_X
CLK_X
LD_Y
LD_X
CAL
G0
G1
A0
A1
A2
A3
A4
A5
A6
A7
A8
D0
D1
D2
Start address for X and Y pointers (LSB)
Start address for X and Y pointers
Start address for X and Y pointers
Start address for X and Y pointers
Start address for X and Y pointers
Start address for X and Y pointers
Start address for X and Y pointers
Start address for X and Y pointers
Start address for X and Y pointers (MSB)
Latch address (A0…A8) to Y start register (0 = track, 1 = hold)
Latch address (A0…A8) to X start register(0 = track, 1 = hold)
Clock YL shift register (shifts on falling edge)
Sets YL shift register to location preloaded in Y start register
Low active (0=sync)
Apply SYNC_YL when CLK_YL is high
Clock X shift register (output valid and s when CLK_X is low)
Sets X shift register to location preloaded in X start register
Low active (0=sync)
Apply SYNC_X when CLK_X is high
After SYNC_X, apply falling edge on CLK_X, and rising edge on CLK_X
Clock YR shift register (shifts on falling edge)
Sets YR shift register to location preloaded in Y start register
Low active (0=sync)
Apply SYNC_YR when CLK_YR is high
Initialize output amplifier
Output amplifier will output BLACKREF in unity gain mode when CAL is high (1)
Apply pulse pattern (one pulse per frame); see
Select output amplifier gain value: G0 = LSB; G1 = MSB
00 = unity gain; 01 = x2; 10 = x4; 11= x8
idem
ADC clock
ADC converts on falling edge
1 = invert output bits
0 = no inversion of output bits
Tristate control of digital ADC outputs
1 = tristate; 0 = output
End-of-scan of YL shift register
Low first clock period after last row (low active)
End-of-scan of X shift register
Low first clock period after last active column (low active)
End-of-scan of YR shift register
Low first clock period after last row (low active)
ADC output bit (LSB)
ADC output bit
ADC output bit
Rev. 7 | www.onsemi.com | Page 16 of 22
Pin Description
Pin Description
Figure 11
NOIS1SM0250A