NOIS1SM0250A-HHC ON Semiconductor, NOIS1SM0250A-HHC Datasheet - Page 13

• Manufacturer Part Number: NOIS1SM0250A-HHC
• Manufacturer: ON Semiconductor

Specifications of NOIS1SM0250A-HHC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 7. Readout Timing Specifications
Loading the X and Y Start Positions
The start positions (start addresses) for region of interest (ROI)
are preloaded in the X or Y start register. They become effective
by the application of the SYNC_X, SYNC_YL and/or SYNC_YR.
The start X or Y address must be applied to their common
address bus and the corresponding LD_X or LD_Y pin must be
pulsed.
On each falling edge of CLK_X, a new pixel of the same row
(line) is accessed. The output stage is in hold when CLK_X is low
and starts generating a new output after a rising edge on CLK_X.
Symbol
T10
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T11
T1
T2
T3
T4
T5
T6
T7
T8
T9
T4 + 40 ns
100 ns
1.8 s
1.8 s
0.4 s
0.1 s
0.8 s
0.1 s
20 ns
40 ns
10 ns
20 ns
10 ns
10 ns
20 ns
10 ns
Min
0
0
–
–
–
–
–
125 ns
0.3 s
0.1 s
0.1 s
0.5 s
0.5 s
40 ns
40 ns
1 s
1 s
2 s
1 s
Typ
–
–
–
–
–
–
–
–
–
–
–
Delay between selection of new row by falling edge on CLK_YL and falling edge on S.
Minimal value. Normally, CLK_YR is low already at the end of the previous sequence.
Delay between selection of new a row by SYNC_YL and falling edge on S.
Duration of S and R pulse.
Duration of RESET pulse.
L/R pulse must overlap second RESET pulse at both sides.
Delay between falling edge on RESET and falling edge on R.
Delay between falling edge on S and rising edge on RESET.
Delay between falling edge on L/R and falling edge on CLK_Y.
Duration of cal pulse. The CAL pulse is given once each frame.
Delay between falling edge of SYNC_YL and rising edge of CAL pulse.
Delay between falling edge on R and rising edge on L/R.
Delay between rising edge of CLK_Y and falling edge on S.
Pulse width SYNC_YL/YR.
Pulse width CLK_YL/YR.
Address setup time.
Load X/Y start register value.
Address stable after load.
SYNC_X pulse width. SYNC_X while CLK_X is high.
Analog output is stable during CLK_X low.
CLK_X pulse width: During this clock phase the analog output ramps to the next pixel
level.
ADC digital output stable after falling edge of CLK_ADC.
Rev. 7 | www.onsemi.com | Page 13 of 22
The following timing constraints apply:
Load the X or Y start addresses in advance, before the X or Y
shift registers are preset by a SYNC pulse. However, if
necessary, they can be loaded just before the SYNC_X or
SYNC_Y pulse as shown in
For example, the X start register can be loaded during the row
idle time. The Y start register can be loaded during readout of the
last row of the previous frame.
If the X or Y start address does not change for later frames, it
does not need to be reloaded in the register.
Description
Figure
12.
NOIS1SM0250A