ADC10DL065EVAL National Semiconductor, ADC10DL065EVAL Datasheet - Page 8

• Manufacturer Part Number: ADC10DL065EVAL
• Manufacturer: National Semiconductor

Specifications of ADC10DL065EVAL

• Lead Free Status / Rohs Status: Not Compliant

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Symbol
t
t
EN
PD
AC Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the
listed test conditions. Operation of the device beyond the maximum Operating Range is not recommended.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TQFP, θ
device under normal operation will typically be about 400 mW (360 typical power consumption + 30 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: Reflow Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤+3.4V to ensure accurate conversions.
Note 8: To guarantee accuracy, it is required that |V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for external reference applications.
Note 14: I
V
voltage, C
Note 15: Excludes I
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
+2.5V, PD = 0V, External V
put mode. Boldface limits apply for T
DR
, and the rate at which the outputs are switching (which is signal dependent). I
JA
n
DR
is 50˚C/W, so P
is total capacitance on the output pin, and f
Data Outputs Active after Hi-Z
Mode
Power Down Mode Exit Cycle
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DR
. See note 14.
D
MAX = 2 Watts at 25˚C and 800 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this
Parameter
A
= 25˚C, and represent most likely parametric norms at the time of characterization. The typical specifications are not guaranteed.
REF
REF
JA
= +1.0V, f
= +1.0V (2V
), and the ambient temperature, (T
J
= T
A
P-P
CLK
–V
n
MIN
D
differential input), the 10-bit LSB is 1.95 mV.
is the average frequency at which that pin is toggling.
J
| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
= 65 MHz, f
to T
1.0 µF on pins 4, 14; 0.1 µF on pins
5,6,12,13; 10 µF between pins 5, 6
and between pins 12, 13
IL
(Continued)
= 0.4V for a falling edge and V
MAX
: all other limits T
IN
A
= 10 MHz, C
), and can be calculated using the formula P
Conditions
8
DR
IN
A
or below GND by more than 100 mV. As an example, if V
<
=V
AGND, or V
A
DR
20148607
or below GND will not damage this device, provided current is limited per
(C
0
x f
L
J
0
= 15 pF/pin, Duty Cycle Stabilizer On, parallel out-
= 25˚C (Notes 7, 8, 9, 12)
IH
+ C
IN
= 2.4V for a rising edge.
>
1
x f
V
A
1
), the current at that pin should be limited to 25 mA. The
+....C
9
x f
(Note 10)
9
Typical
) where V
10
1
D
MAX = (T
DR
A
is the output driver power supply
(Note 10)
= V
J
Limits
max - T
D
A
= +3.3V, V
is +3.3V, the full-scale
A
)/θ
JA
. In the 64-pin
(Limits)
Units
J
DR
max, the
ns
µs
=