ADC10DL065EVAL National Semiconductor, ADC10DL065EVAL Datasheet - Page 19

• Manufacturer Part Number: ADC10DL065EVAL
• Manufacturer: National Semiconductor

Specifications of ADC10DL065EVAL

• Lead Free Status / Rohs Status: Not Compliant

Applications Information
Where dev is the angular difference in degrees between the
two signals having a 180˚ relative phase relationship to each
other (see Figure 3). Drive the analog inputs with a source
impedance less than 100Ω.
For differential operation, each analog input pin of the differ-
ential pair should have a peak-to-peak voltage equal to the
reference voltage, V
each other and be centered around V
1.3.1 Single-Ended Operation
Performance with differential input signals is better than with
single-ended signals. For this reason, single-ended opera-
tion is not recommended. However, if single ended-operation
is required and the resulting performance degradation is
acceptable, one of the analog inputs should be connected to
the d.c. mid point voltage of the driven input. The peak-to-
peak differential input signal at the driven input pin should be
twice the reference voltage to maximize SNR and SINAD
performance (Figure 2b). For example, set V
bias V
to 1.5V.
Because very large input signal swings can degrade distor-
tion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
when maintaining a full-range output. Table 1 and Table 2
indicate the input to output relationship of the ADC10DL065.
TABLE 1. Input to Output Relationship – Differential
V
V
V
V
V
V
V
V
FIGURE 3. Angular Errors Between the Two Input
V
V
REF
REF
REF
REF
Signals Will Reduce the Output Level or Cause
CM
CM
CM
CM
CM
IN +
IN
/2
/4
/4
/2
−
−
+
+
− to 1.0V and drive V
V
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
CM
CM
CM
CM
IN −
CM
/2
/4
/4
/2
+
+
−
−
REF
Binary Output
00 0000 0000
01 0000 0000
10 0000 0000
11 0000 0000
11 1111 1111
, be 180 degrees out of phase with
Distortion
Input
IN
+ with a signal range of 0.5V
20148612
CM
2’s Complement
.
10 0000 0000
11 0000 0000
00 0000 0000
01 0000 0000
01 1111 1111
(Continued)
Output
REF
to 0.5V,
19
1.3.2 Driving the Analog Inputs
The V
an analog switch followed by a switched-capacitor amplifier.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As the driving source attempts
to counteract these voltage spikes, it may add noise to the
signal at the ADC analog input. To help isolate the pulses at
the ADC input from the amplifier output, use RCs at the
inputs, as can be seen in Figure 4. These components
should be placed close to the ADC inputs because the input
pins of the ADC is the most sensitive part of the system and
this is the last opportunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. For wide-
band undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency to
maintain a linear delay response. The values of the RC
shown in Figure 4 are suitable for applications with input
frequencies up to approximately 70MHz.
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
range of 0.5V to 2.0V and be a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than 2.6V. See Section 1.2
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, OEA,
OEB, PD, DF/DCS, and MULTIPLEX.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 15 MHz to 65 MHz. The higher the input
frequency, the more critical it is to have a low jitter clock.The
trace carrying the clock signal should be as short as possible
and should not cross any other signal line, analog or digital,
not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency too low, the charge on
internal capacitors can dissipate to the point where the ac-
curacy of the output data will degrade. This is what limits the
lowest sample rate.
The clock line should be terminated at its source in the
characteristic impedance of that line. Take care to maintain a
TABLE 2. Input to Output Relationship – Single-Ended
V
V
V
V
V
V
V
V
V
V
REF
REF
CM
CM
CM
CM
REF
REF
IN +
CM
IN
/2
/2
+ and the V
−
−
+
+
V
V
V
V
V
V
CM
CM
CM
CM
CM
IN −
IN
− inputs of the ADC10DL065 consist of
Binary Output
00 0000 0000
01 0000 0000
10 0000 0000
11 0000 0000
11 1111 1111
Input
CM
2’s Complement
, should be in the
10 0000 0000
11 0000 0000
00 0000 0000
01 0000 0000
01 1111 1111
Output
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