ADC10DL065EVAL National Semiconductor, ADC10DL065EVAL Datasheet - Page 20

• Manufacturer Part Number: ADC10DL065EVAL
• Manufacturer: National Semiconductor

Specifications of ADC10DL065EVAL

• Lead Free Status / Rohs Status: Not Compliant

www.national.com
Applications Information
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on
setting characteristic impedance.
It is highly desirable that the the source driving the ADC CLK
pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground, as shown in Figure 4, such that
the resistor value is equal to the characteristic impedance of
the clock line and the capacitor value is
where t
"L" is the line length and Z
of the clock line. This termination should be as close as
possible to the ADC clock pin but beyond it as seen from the
clock source. Typical t
FR-4 board material. The units of "L" and t
same (inches or centimeters).
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC10DL065 has a Duty Cycle Stabi-
lizer which can be enabled using the DF/DCS pin. It is
designed to maintain performance over a clock duty cycle
range of 20% to 80% at 65 MSPS. The Duty Cycle Stabilizer
circuit requires a fast clock edge to produce the internal
clock, which is the reason for the rise and fall time require-
ment listed in the specifications table.
2.2 OEA, OEB
The OEA and OEB pins, when high, put the output pins of
their respective converters into a high impedance state.
When either of these pin is low, the corresponding outputs
are in the active state. The ADC10DL065 will continue to
convert whether these pins are high or low, but the output
can not be read while the pin is high.
Since ADC noise increases with increased output capaci-
tance at the digital output pins, do not use the TRI-STATE
outputs of the ADC10DL065 to drive a bus. Rather, each
output pin should be located close to and drive a single
digital input pin. To further reduce ADC noise, a 100 Ω
resistor in series with each ADC digital output pin, located
close to their respective pins, should be added to the circuit.
2.3 PD
The PD pin, when high, holds the ADC10DL065 in a power-
down mode to conserve power when the converter is not
being used. The power consumption in this state is 36 mW
with a 65MHz clock and 40mW if the clock is stopped when
PD is high. The output data pins are undefined and the data
in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 4, 5, 6, 12, 13 and 14 and
is about 500 µs with the recommended components on the
V
loose their charge in the Power Down mode and must be
recharged by on-chip circuitry before conversions can be
accurate. Smaller capacitor values allow slightly faster re-
covery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
RP
, V
RM
PD
and V
is the signal propagation rate down the clock line,
RN
reference bypass pins. These capacitors
PD
is about 150 ps/inch (60 ps/cm) on
O
is the characteristic impedance
PD
(Continued)
should be the
20
2.4 DF/DCS
Duty cycle stabilization and output data format are select-
able using this quad state function pin. When enabled, duty
cycle stabilization can compensate for clock inputs with duty
cycles ranging from 20% to 80% and generate a stable
internal clock, improving the performance of the part. The
Duty Cycle Stabilizer circuit requires a fast clock edge to
produce the internal clock, which is the reason for the rise
and fall time requirement listed in the specifications table.
With DF/DCS = V
duty cycle stabilization is applied to the clock. With DF/DCS
= 0 the output data format is 2’s complement and duty cycle
stabilization is applied to the clock. With DF/DCS = V
V
cycle stabilization is not used. If DF/DCS is floating, the
output data format is offset binary and duty cycle stabiliza-
tion is not used. While the sense of this pin may be changed
"on the fly," doing this is not recommended as the output
data could be erroneous for a few clock cycles after this
change is made.
2.5 MULTIPLEX
With the MULTIPLEX pin at a logic low, the digital output
words from channels A and B are available on separate
digital output buses (Parallel mode). When MULTIPLEX is
high, the digital output words are multiplexed on pins
DA0:DA9 (Multiplex Mode). The ABb pin changes synchro-
nously with the multiplexed outputs, and is high when chan-
nel A data is present on the outputs, and low when channel
B data is present.
3.0 OUTPUTS
The ADC10DL065 has 10 TTL/CMOS compatible Data Out-
put pins for each output. Valid data is present at these
outputs while the OE and PD pins are low. In the parallel
mode, the data should be captured with the CLK signal.
Depending on the setup and hold time requirements of the
receiving circuit (ASIC), either the rising edge or the falling
edge of the CLK signal can be used to latch the data.
Generally, rising-edge- -capture would maximize setup time
with minimal hold time; while falling-edge-capture would
maximize hold time with minimal setup time. However, actual
timing for the falling-edge case depends greatly on the CLK
frequency and both cases also depend on the delays inside
the ASIC. Refer to the Tod spec in the AC Electrical Charac-
terisitics table.
In Multiplex mode, both channel outputs are available on
DA0:DA9. The ABb signal is available to de-multiplex the
output bus. The ABb signal may also be used to latch the
data in the ASIC thus avoiding the use of the CLK signal
altogether. However, since the ABb signal edges are pro-
vided in-phase with the data transitions, generally the ASIC
circuitry would have to delay the ABb signal with respect to
the data in order to use it as the clock for the capturing
latches. It is also possible to use the CLK signal to latch the
data in the multiplexed mode as well - as described in the
previous paragraph.
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally,
bus capacitance beyond the specified 15 pF/pin will cause
RM
B the output data format is 2’s complement and duty
DR
and DR GND. These large charging current
A
the output data format is offset binary and
RM
A or