ADC10DL065EVAL National Semiconductor, ADC10DL065EVAL Datasheet - Page 18

• Manufacturer Part Number: ADC10DL065EVAL
• Manufacturer: National Semiconductor

Specifications of ADC10DL065EVAL

• Lead Free Status / Rohs Status: Not Compliant

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Functional Description
Operating on a single +3.3V supply, the ADC10DL065 uses
a pipeline architecture and has error correction circuitry to
help ensure maximum performance. The differential analog
input signal is digitized to 10 bits. The user has the choice of
using an internal 1.0 Volt or 0.5 Volt stable reference, or
using an external reference. Any external reference is buff-
ered on-chip to ease the task of driving that pin.
The output word rate is the same as the clock frequency,
which can be between 15 MSPS and 65 MSPS (typical) with
fully specified performance at 65 MSPS. The analog input for
both channels is acquired at the rising edge of the clock and
the digital data for a given sample is delayed by the pipeline
for 7 clock cycles. Duty cycle stabilization and output data
format are selectable using the quad state function DF/DCS
pin. The output data can be set for offset binary or two’s
complement.
A logic high on the power down (PD) pin reduces the con-
verter power consumption to 36 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC10DL065:
1.1 Analog Inputs
There is one reference input pin, V
select an internal reference, or to supply an external refer-
ence. The ADC10DL065 has two analog signal input pairs,
V
for the other converter. Each pair of pins forms a differential
input pair.
1.2 Reference Pins
The ADC10DL065 is designed to operate with an internal
1.0V or 0.5V reference, or an external 1.0V reference, but
performs well with extermal reference voltages in the range
of 0.8V to 1.2V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC10DL065. Increasing
the reference voltage (and the input signal swing) beyond
1.2V may degrade THD for a full-scale input, especially at
higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects
of noise currents in the ground path.
The six Reference Bypass Pins (V
V
All these pins should each be bypassed to ground with a 0.1
µF capacitor. A 10 µF capacitor should be placed between
the V
pins, as shown in Figure 4. This configuration is necessary to
avoid reference oscillation, which could result in reduced
SFDR and/or SNR.
Smaller capacitor values than those specified will allow
faster recovery from the power down mode, but may result in
IN
RM
3.0V ≤ V
V
2.4V ≤ V
15 MHz ≤ f
0.8V ≤ V
0.5V ≤ V
D
A+ and V
B and V
RP
= V
A and V
A
A
DR
REF
CM
RN
≤ 3.6V
CLK
IN
≤ V
≤ 2.0V
B) are made available for bypass purposes.
≤ 1.2V (for an external reference)
A- for one converter and V
RN
≤ 65 MHz
A
A pins and between the V
RP
A, V
REF
, which is used to
RM
IN
A, V
RP
B+ and V
B and V
RN
A, V
IN
RP
RN
B-
B,
B
18
degraded noise performance. Loading any of these pins
other than V
radation.
The nominal voltages for the reference bypass pins are as
follows:
User choice of an on-chip or external reference voltage is
provided. The internal 1.0 Volt reference is in use when the
the V
connected to AGND, the internal 0.5 Volt reference is in use.
If a voltage in the range of 0.8V to 1.2V is applied to the V
pin, that is used for the voltage reference. When an external
reference is used, the V
ground with a 0.1 µF capacitor close to the reference input
pin. There is no need to bypass the V
internal reference is used.
1.3 Signal Inputs
The signal inputs are V
V
defined as
for the "A" converter and
for the "B" converter. Figure 2 shows the expected input
signal range. Note that the common mode input voltage,
V
The peaks of the individual input signals should each never
exceed 2.6V.
The ADC10DL065 performs best with a differential input
signal with each input centered around a common mode
voltage, V
log input pin should not exceed the value of the reference
voltage or the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For complex waveforms, however,
angular errors will result in distortion.
For single frequency sine waves the full scale error in LSB
can be described as approximately
IN
CM
V
V
V
B+ and V
RM
RP
RN
, should be in the range of 0.5V to 2.0V.
REF
= V
= V
= 1.5 V
FIGURE 2. Expected Input Signal Range
CM
pin is connected to V
RM
RM
RM
IN
. The peak-to-peak voltage swing at each ana-
E
+ V
− V
B− for the other ADC . The input signal, V
FS
A and V
V
V
REF
REF
= 1024 ( 1 - sin (90˚ + dev))
IN
IN
A = (V
B = (V
/ 2
/ 2
RM
IN
B may result in performance deg-
REF
A+ and V
IN
IN
A+) – (V
B+) – (V
pin should be bypassed to
A
. When the V
IN
IN
IN
A− for one ADC and
A−)
B−)
20148611
REF
pin when the
REF
pin is
IN
REF
, is