ADC1113D125WO/DB,598 NXP Semiconductors, ADC1113D125WO/DB,598 Datasheet - Page 34

• Manufacturer Part Number: ADC1113D125WO/DB,598
• Description: BOARD EVALADC1113D125 WO/FPGA
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1113D125WO/DB,598

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial JESD204A
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 690mW @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1113D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6893

NXP Semiconductors
Table 50.
Default values are highlighted.
Table 51.
Default values are highlighted.
ADC1113D125
Product data sheet
Bit
0
Bit
7
6
5 to 4
3
2
1
0
Symbol
LANE_PD
Symbol
-
SCR_IN_MODE
LANE_MODE[1:0]
-
LANE_POL
LANE_CLK_POS_EDGE R/W
Lane_PD
Lane0_0_ctrl (address 0870h)
Lane2_0_ctrl (address 0871h)
R/W
R/W
R/W
R/W
R/W
Access
Access
-
-
All information provided in this document is subject to legal disclaimers.
…continued
Value
0
1
Value
0
0 (reset)
1
00 (reset)
01
10
11
0
0
1
0
1
0
1
Rev. 3 — 10 February 2011
Description
lane power-down control:
Description
not used
defines the input type for scrambler and 8b/10b units:
defines output type of lane output unit:
not used
defines lane polarity:
defines lane clock polarity:
lane power-down control:
lane is operational
lane is in Power-down mode
(normal mode) = input of the scrambler and 8b/10b units is
the output of the Frame Assembly unit.
input of the scrambler and 8b/10b units is the PRBS generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_Ctrl
register)
normal mode: lane output is the 8-bit/10-bit output unit
constant mode: lane output is set to a constant (0x0)
toggle mode: lane output is toggling between 0x0 and 0x1
PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
lane polarity is normal
lane polarity is inverted
lane clock provided to the serializer is active on positive
edge
lane clock provided to the serializer is active on negative edge
lane is operational
lane is in Power-down mode
Dual 11-bit ADC; serial JESD204A interface
ADC1113D125
© NXP B.V. 2011. All rights reserved.
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