ADC1113D125WO/DB,598 NXP Semiconductors, ADC1113D125WO/DB,598 Datasheet - Page 31

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ADC1113D125WO/DB,598

Manufacturer Part Number
ADC1113D125WO/DB,598
Description
BOARD EVALADC1113D125 WO/FPGA
Manufacturer
NXP Semiconductors
Series
-r

Specifications of ADC1113D125WO/DB,598

Number Of Adc's
2
Number Of Bits
11
Sampling Rate (per Second)
125M
Data Interface
Serial JESD204A
Input Range
1 ~ 2 Vpp
Power (typ) @ Conditions
690mW @ 125MSPS
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC1113D125
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-6893
NXP Semiconductors
Table 33.
Default values are highlighted.
Table 34.
Default values are highlighted.
Table 35.
Default values are highlighted.
Table 36.
Default values are highlighted.
Table 37.
Default values are highlighted.
Table 38.
Default values are highlighted.
Table 39.
Default values are highlighted.
ADC1113D125
Product data sheet
Bit
7
6 to 0
Bit
7 to 0
Bit
7 to 2
1 to 0
Bit
7 to 0
Bit
7 to 4
3 to 0
Bit
7
6 to 1
0
Bit
7 to 3
2 to 0
Symbol
-
LSB_INIT[6:0]
Symbol
MSB_INIT[7:0]
Symbol
-
PRBS_TYPE[1:0]
Symbol
DID[7:0]
Symbol
-
BID[3:0]
Symbol
SCR
-
L
Symbol
-
F[2:0]
Ser_ScramblerA (address 0809h)
Ser_ScramblerB (address 080Ah)
Ser_PRBS_Ctrl (address 080Bh)
Cfg_0_DID (address 0820h)
Cfg_1_BID (address 0821h)
Cfg_3_SCR_L (address 0822h)
Cfg_4_F (address 0823h)
-
R/W
-
R/W
Access
-
R/W
Access
R/W
Access
Access
R
Access
-
R/W
Access
R/W
R/W
Access
-
All information provided in this document is subject to legal disclaimers.
Value
0
0000000
Value
11111111
Value
000000
00 (reset)
01
10
11
Value
11101101 defines the device (= link) identification number
Value
0000
1010
Value
0
000000
0
Value
00000
001
Rev. 3 — 10 February 2011
Description
not used
defines the initialization vector for the scrambler polynomial
(lower)
Description
defines the initialization vector for the scrambler polynomial
(upper)
Description
not used
defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
Description
Description
not used
defines the bank ID – extension to DID
Description
scrambling enabled
not used
defines the number of lanes per converter device, minus 1
Description
not used
defines the number of octets per frame, minus 1
PRBS-7
PRBS-7
PRBS-23
PRBS-31
Dual 11-bit ADC; serial JESD204A interface
ADC1113D125
© NXP B.V. 2011. All rights reserved.
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