ADC1113D125WO/DB,598 NXP Semiconductors, ADC1113D125WO/DB,598 Datasheet - Page 30

• Manufacturer Part Number: ADC1113D125WO/DB,598
• Description: BOARD EVALADC1113D125 WO/FPGA
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1113D125WO/DB,598

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial JESD204A
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 690mW @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1113D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6893

NXP Semiconductors
Table 30.
Default values are highlighted.
Table 31.
Default values are highlighted.
Table 32.
Default values are highlighted.
ADC1113D125
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
7 to 2
1
0
Bit
7 to 3
2 to 0
Symbol
-
TRISTATE_CFG_PINS
SYNC_POL
SYNC_SINGLE_ENDED R/W
-
REV_SCR
REV_ENCODER
REV_SERIAL
Symbol
-
SWAP_LANE_1_2
SWAP_ADC_0_1
Symbol
-
SWING_SEL[2:0]
Ser_Control1 (address 0805h)
Ser_Control2 (address 0806h)
Ser_Analog_Ctrl (address 0808h)
R/W
R/W
-
-
-
-
Access
-
-
Access
R/W
R/W
Access
-
R/W
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
1
0
1
0
1
0
1
Value
000000
0
1
0
1
Value
00000
011
Rev. 3 — 10 February 2011
LSBs are swapped with MSBs at the 8-bit/10-bit encoder input:
LSBs are swapped with MSBs at the lane input:
Description
not used
pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
defines the sync signal polarity:
defines the input mode of the sync signal:
not used
LSBs are swapped with MSBs at the scrambler input:
Description
not used
outputs of the JESD204A unit are swapped. (Output buffer A is
connected to Lane 1, Output buffer B is connected to Lane 0):
inputs of the JESD204A unit are swapped. (ADC A output is
connected to Input B, ADC B is connected to Input A):
Description
not used
defines the swing of output buffers A and B
synchronization signal is active LOW
synchronization signal is active HIGH
synchronization input mode is set in Differential mode
synchronization input mode is set in Single-ended mode
disable
enable
disable
enable
disable
enable
disable
enable
disable
enable
Dual 11-bit ADC; serial JESD204A interface
ADC1113D125
© NXP B.V. 2011. All rights reserved.
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