ADC1113D125WO/DB,598 NXP Semiconductors, ADC1113D125WO/DB,598 Datasheet
ADC1113D125WO/DB,598
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ADC1113D125WO/DB,598 Summary of contents
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ADC1113D125 Dual 11-bit ADC; serial JESD204A interface Rev. 3 — 10 February 2011 1. General description The ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power at a sample rate of 125 Msps. ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Sampling frequency (Msps) ADC1113D125HN/C1 125 5. Block diagram INAP T/H INPUT STAGE INAM CLKP DLL PLL CLKM INBP T/H INPUT STAGE INBM ADC1113D Fig 1. Block diagram ADC1113D125 Product data sheet Dual 11-bit ADC; serial JESD204A interface ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol INAP INAM VCMA REFAT REFAB AGND CLKP CLKM AGND REFBB REFBT VCMB INBM ADC1113D125 Product data sheet 1 INAP INAM 2 VCMA 3 REFAT 4 5 REFAB 6 AGND CLKP 7 CLKM 8 AGND 9 10 REFBB ...
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... NXP Semiconductors Table 2. Symbol INBP VDDA VDDA SCLK SDIO CS AGND RESET SCRAMBLER CFG0 CFG1 CFG2 CFG3 VDDD DGND DGND DGND VDDD CMLPB CMLNB VDDD DGND DGND VDDD CMLNA CMLPA VDDD DGND DGND SYNCP SYNCN DGND VDDD SWING_0 SWING_1 DNC VDDA AGND ...
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... NXP Semiconductors Table 2. Symbol VDDA SENSE VREF VDDA [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. [2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” Limiting values Table 3. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics Symbol Parameter Supplies V analog supply voltage DDA V digital supply voltage DDD I analog supply current DDA I digital supply current DDD P total power dissipation tot P power dissipation Clock inputs: pins CLKP and CLKM (AC-coupled) Low-Voltage Positive Emitter-Coupled Logic (LVPECL) ...
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... NXP Semiconductors Table 5. Static characteristics Symbol Parameter Analog inputs: pins INAP, INAM, INBP, and INBM I input current I R input resistance I C input capacitance I V common-mode input I(cm) voltage B input bandwidth i V differential input voltage I(dif) Voltage controlled regulator output: pins VCMA and VCMB ...
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... NXP Semiconductors Table 5. Static characteristics Symbol Parameter Serial configuration: pins SYNCCP, SYNCCN V LOW-level input voltage IL V HIGH-level input voltage differential; input IH Accuracy INL integral non-linearity DNL differential non-linearity E offset error offset E gain error G M channel-to-channel gain G(CTC) matching Supply PSRR power supply rejection ...
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... NXP Semiconductors 10. Dynamic characteristics 10.1 Dynamic characteristics Table 6. Dynamic characteristics Symbol Parameter Analog signal processing α second harmonic level 2H α third harmonic level 3H THD total harmonic distortion ENOB effective number of bits SNR signal-to-noise ratio SFDR spurious-free dynamic range IMD intermodulation distortion α ...
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... NXP Semiconductors 10.2 Clock and digital output timing [1] Table 7. Characteristics Symbol Parameter Clock timing input: pins CLKP and CLKM f clock frequency clk t data latency time lat(data) δ clock duty cycle clk t sampling delay time d(s) t wake-up time wake [1] Typical values measured at V DDA = − ...
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... NXP Semiconductors Fig 4. 10.4 SPI timing Table 8. Symbol Serial Peripheral Interface timing t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V values are across the full temperature range T (INAP, INBP) − outputs; unless otherwise specified. Fig 5. ADC1113D125 Product data sheet Eye diagram receiver common-mode ...
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... NXP Semiconductors 11. Application information 11.1 Analog inputs 11.1.1 Input stage description The analog input of the ADC1113D125 supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (V The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) ...
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... NXP Semiconductors Fig 7. The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 9. Input frequency (MHz) 11.1.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 8. ADC1113D125 Product data sheet ...
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... NXP Semiconductors Fig 9. The configuration shown in both cases, the choice of transformer is a compromise between cost and performance. 11.2 System reference and power management 11.2.1 Internal/external reference The ADC1113D125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF an SENSE (see control bits INTREF[2:0] (when bit INTREF_EN = logic 1 ...
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... NXP Semiconductors VREF SENSE Fig 10. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 10. Mode Internal Internal External Internal, SPI mode (Figure ADC1113D125 Product data sheet REFERENCE AMP EXT_ref BUFFER SELECTION LOGIC Table 10. ...
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... NXP Semiconductors VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 11. Internal reference (p-p) full-scale VREF 0.1 μF V SENSE VDDA Fig 13. External reference (p- (p-p) full-scale Figure 11 required reference voltage source. 11.2.2 Programmable full-scale The full-scale is programmable between 1 V (p- (p-p) (see Table 11. INTREF[2:0] 000 ...
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... NXP Semiconductors 11.2.3 Common-mode output voltage (V An 0.1 μF filter capacitor should be connected between the pins VCMA and VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point ...
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... NXP Semiconductors a. Sine clock input c. LVPECL clock input Fig 17. Differential clock input 11.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via 5 kΩ internal resistors. Fig 18. Equivalent input circuit ADC1113D125 Product data sheet ...
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... NXP Semiconductors Single-ended or differential clock inputs can be selected via the SPI (see single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 11.3.3 Clock input divider The ADC1113D125 contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV2_SEL = logic 1 ...
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... NXP Semiconductors Fig 20. CML output connection to the receiver (AC-coupled) 11.5 JESD204A serializer For more information about the JESD204A standard refer to the JEDEC web site. 11.5.1 Digital JESD204A formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard. This ensures signal integrity and guarantees the clock and the data recovery at the receiver side ...
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... NXP Semiconductors ADC_MODE[1:0] PRBS 11 N DUMMY & CS ADC_PD ADC A × 1 frame CLK PLL × F AND character CLK ASSEMBLY DLL × 10F bit CLK ADC ADC_PD & DUMMY CS 11 PRBS ADC_MODE[1:0] Fig 22. Detailed view of the JESD204A serializer with debug functionality 11.5.2 ADC core output codes versus input voltage Table 13 Table 13 ...
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... NXP Semiconductors Table 13. − INP +0.9970703 +0.9980469 +0.9990234 +1.0000000 > +1 11.6 Serial Peripheral Interface (SPI) 11.6.1 Register description The ADC1113D125 serial interface is a synchronous serial communications port allowing for easy interfacing with many industry microprocessors. It provides access to the registers that control the operation of the chip in both read and write modes. ...
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... NXP Semiconductors The steps involved in a data transfer are as follows: 1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits ...
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Table 17. Register allocation map [1] Address Register name Access (hex) Bit 7 ADC control registers 0003 Channel index R/W - 0005 Reset and R/W SW_RST Power-down modes 0006 Clock R/W - 0007 Vref R/W - 0013 Offset R/W - ...
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Table 17. Register allocation map …continued [1] Address Register name Access (hex) Bit 7 0826 Cfg_7_CS_N R/W* 0 0827 Cfg_8_Np R/W 0 0828 Cfg_9_S R/W* 0 0829 Cfg_10_HD_CF R/W* HD 082C Cfg_01_2_LID R/W* 0 082D Cfg_02_2_LID R/W* 0 084C Cfg01_13_FCHK ...
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... NXP Semiconductors 11.6.3 Register description 11.6.3.1 ADC control registers Table 18. Register Channel Index (address 0003h) Default values are highlighted. Bit Symbol Access ADCB R/W 0 ADCA R/W Table 19. Register Reset and Power-down mode (address 0005h) Default values are highlighted. Bit Symbol Access ...
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... NXP Semiconductors Table 21. Register Vref (address 0008h) Default values are highlighted. Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 22. Digital offset adjustment (address 0013h) Default values are highlighted. Register offset: Decimal +31 ... 0 ... −32 Table 23. Register Test pattern 1 (address 0014h) Default values are highlighted. ...
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... NXP Semiconductors Table 24. Register Test pattern 2 (address 0015h) Default values are highlighted. Bit Symbol Access TESTPAT_2[10:3] R/W Table 25. Register Test pattern 3 (address 0016h) Default values are highlighted. Bit Symbol Access TESTPAT_3[2:0] R/W 11.6.4 JESD204A digital control registers Table 26. Ser_Status (address 0801h) Default values are highlighted ...
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... NXP Semiconductors Table 28. Ser_Cfg_Setup (address 0803h) Default values are highlighted. Bit Symbol CFG_SETUP[3:0] Table 29. JESD204A configuration table CFG_SETUP[3:0] ADC A ADC B Lane 0 0 0000 0001 0010 0011 ON OFF 4 0100 OFF ON 5 0101 ON OFF 6 0110 ON OFF 7 0111 OFF ON 8 1000 OFF ON 9 1001 ...
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... NXP Semiconductors Table 30. Ser_Control1 (address 0805h) Default values are highlighted. Bit Symbol TRISTATE_CFG_PINS 5 SYNC_POL 4 SYNC_SINGLE_ENDED R REV_SCR 1 REV_ENCODER 0 REV_SERIAL Table 31. Ser_Control2 (address 0806h) Default values are highlighted. Bit Symbol SWAP_LANE_1_2 0 SWAP_ADC_0_1 Table 32. Ser_Analog_Ctrl (address 0808h) Default values are highlighted. Bit Symbol SWING_SEL[2:0] ...
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... NXP Semiconductors Table 33. Ser_ScramblerA (address 0809h) Default values are highlighted. Bit Symbol LSB_INIT[6:0] Table 34. Ser_ScramblerB (address 080Ah) Default values are highlighted. Bit Symbol MSB_INIT[7:0] Table 35. Ser_PRBS_Ctrl (address 080Bh) Default values are highlighted. Bit Symbol PRBS_TYPE[1:0] Table 36. Cfg_0_DID (address 0820h) Default values are highlighted. ...
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... NXP Semiconductors Table 40. Cfg_5_K (address 0824h) Default values are highlighted. Bit Symbol K[4:0] Table 41. Cfg_6_M (address 0825h) Default values are highlighted. Bit Symbol Table 42. Cfg_7_CS_N (address 0826h) Default values are highlighted. Bit Symbol CS[ N[3:0] Table 43. Cfg_8_Np (address 0827h) Default values are highlighted. ...
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... NXP Semiconductors Table 47. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit Symbol LID[4:0] Table 48. Cfg01_13_fchk (address 084Ch) Default values are highlighted. Bit Symbol FCHK[7:0] Table 49. Cfg02_13_fchk (address 084Dh) Default values are highlighted. Bit Symbol FCHK[7:0] Table 50. Lane0_0_ctrl (address 0870h) Default values are highlighted. ...
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... NXP Semiconductors Table 50. Lane0_0_ctrl (address 0870h) Default values are highlighted. Bit Symbol 0 LANE_PD Table 51. Lane2_0_ctrl (address 0871h) Default values are highlighted. Bit Symbol SCR_IN_MODE LANE_MODE[1: LANE_POL 1 LANE_CLK_POS_EDGE R/W 0 Lane_PD ADC1113D125 Product data sheet …continued Access Value Description R/W lane power-down control: ...
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... NXP Semiconductors Table 52. ADCA_0_ctrl (address 0890h) Default values are highlighted. Bit Symbol ADC_MODE[1: ADC_PD Table 53. ADCB_0_ctrl (address 0891h) Default values are highlighted. Bit Symbol ADC_MODE[1: ADC_PD ADC1113D125 Product data sheet Access Value Description - 00 not used R/W defines input type of JESD204A unit: ...
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... NXP Semiconductors 12. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 0.85 mm terminal 1 index area terminal 1 56 index area Dimensions (1) Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Abbreviations Table 54. Acronym ADC DCS ESD IF IMD LSB LVCMOS LVPECL MSB OTR PRBS SFDR SNR SPI TX ADC1113D125 Product data sheet Abbreviations Description Analog-to-Digital Converter Duty Cycle Stabilizer ElectroStatic Discharge Intermediate Frequency InterModulation Distortion Least Significant Bit Low Voltage Complementary Metal Oxide Semiconductor ...
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... NXP Semiconductors 14. Revision history Table 55. Revision history Document ID ADC1113D125 v.3 Modifications: ADC1113D125 v.2 ADC1113D125 v.1 ADC1113D125 Product data sheet Release date Data sheet status 20110210 Product data sheet • Data sheet status changed from Preliminary to Product. • Text and drawings updated throughout entire data sheet. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.2 Clock and digital output timing . . . . . . . . . . . . 10 10 ...