ADC1113D125WO/DB,598 NXP Semiconductors, ADC1113D125WO/DB,598 Datasheet - Page 17

• Manufacturer Part Number: ADC1113D125WO/DB,598
• Description: BOARD EVALADC1113D125 WO/FPGA
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1113D125WO/DB,598

• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial JESD204A
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 690mW @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1113D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6893

NXP Semiconductors
ADC1113D125
Product data sheet
11.2.3 Common-mode output voltage (V
11.2.4 Biasing
11.3.1 Drive modes
11.3 Clock input
An 0.1 μF filter capacitor should be connected between the pins VCMA and VCMB and
ground to ensure a low-noise common-mode output voltage. When AC-coupled, these
pins can be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
The common-mode input voltage, V
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
The ADC1113D125 can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
Fig 16. LVCMOS single-ended clock input
a. Rising edge LVCMOS
0.1 μF
VCMA
VCMB
clock input
1.5 V
LVCMOS
All information provided in this document is subject to legal disclaimers.
PACKAGE
Rev. 3 — 10 February 2011
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CLKM
CLKP
ESD
I(cm)
PARASITICS
O(cm)
, at the inputs to the sample-and-hold stage
Dual 11-bit ADC; serial JESD204A interface
)
b. Falling edge LVCMOS
COMMON MODE
REFERENCE
clock input
LVCMOS
ADC1113D125
ADC CORE
© NXP B.V. 2011. All rights reserved.
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CLKM
CLKP
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