EVAL-ADF7023-JDB2Z Analog Devices Inc, EVAL-ADF7023-JDB2Z Datasheet - Page 62

• Manufacturer Part Number: EVAL-ADF7023-JDB2Z
• Description: BOARD EVAL ADF7023-JDB2Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB2Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

ADF7023-J
DOWNLOADABLE FIRMWARE MODULES
The program RAM memory of the ADF7023-J can be used to
store firmware modules for the communications processor that
provide the ADF7023-J with extra functionality. The binary
code for these firmware modules and details on their functionality
are available from Analog Devices. These firmware modules are
included in the Applications Software, which is available online
at ftp://ftp.analog.com/pub/RFL/ADF7023/. Three modules are
briefly described in this section: image rejection calibration,
AES encryption and decryption, and Reed-Solomon coding.
WRITING A MODULE TO PROGRAM RAM
The sequence to write a firmware module to program RAM is
as follows:
1.
2.
3.
4.
5.
The firmware module is now stored on program RAM.
IMAGE REJECTION CALIBRATION MODULE
The calibration system initially disables the ADF7023-J receiver,
and an internal RF source is applied to the RF input at the
image frequency. The algorithm then maximizes the receiver
image rejection performance by iteratively minimizing the
quadrature gain and phase errors in the polyphase filter.
The calibration algorithm takes its initial estimates for quadrature
phase correction (Address 0x118) and quadrature gain correction
(Address 0x119) from BBRAM. After calibration, new optimum
values of phase and gain are loaded back into these locations.
These calibration values are maintained in BBRAM during
sleep mode and are automatically reapplied from a wake-up
event, which keeps the number of calibrations required to a
minimum.
Depending on the initial values of quadrature gain and phase
correction, the calibration algorithm can take approximately 20 ms
to find the optimum image rejection performance. However, the
calibration time can be significantly less than this when the seed
values used for gain and phase correction are close to optimum.
The image rejection performance is also dependent on temperature.
To maintain optimum image rejection performance, a calibration
should be activated whenever a temperature change of more than
10°C occurs. The ADF7023-J on-chip temperature sensor can
be used to determine when the temperature exceeds this limit.
To run the IR calibration, issue a CMD_IR_CAL (Register 0xBD).
In order for this to work successfully, ensure that the BB filter
calibration is enabled in the MODE_CONTROL register
(Address 0x11A).
Ensure that the ADF7023-J is in PHY_OFF.
Issue the CMD_RAM_LOAD_INIT command.
Write the module to program RAM using an SPI memory
block write (see the SPI Interface section).
Issue the CMD_RAM_LOAD_DONE command.
Issue the CMD_SYNC command.
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AES ENCRYPTION AND DECRYPTION MODULE
The downloadable AES firmware module supports 128-bit block
encryption and decryption with key sizes of 128 bits, 192 bits,
and 256 bits. Two modes are supported: ECB mode and CBC
Mode 1. ECB mode simply encrypts/decrypts on a 128-bit block
by block with a single secret key as illustrated in Figure 76. CBC
Mode 1 encrypts after first adding (Modulo 2), a 128-bit user-
supplied initialization vector. The resulting cipher text is then
used as the initialization vector for the next block and so forth,
as illustrated in Figure 77. Decryption provides the inverse
functionality. The firmware also takes advantage of an on-chip
hardware accelerator module to enhance throughput and minimize
the latency of the AES processing.
REED-SOLOMON CODING MODULE
This coding module uses Reed-Solomon block coding to detect
and correct errors in the received packet. A transmit message of
k bytes in length is appended with an error checking code (ECC) of
length n − k bytes to give a total message length of n bytes, as
shown in Figure 75.
The receiver decodes the ECC to detect and correct up to t bytes
in error, where t = (n − k)/2. The firmware supports correction
of up to five bytes in the n byte field. To correct t bytes in error,
an ECC length of 2t bytes is required, and the byte errors can be
randomly distributed throughout the payload and ECC fields.
Reed-Solomon coding exhibits excellent burst error correction
capability and is commonly used to improve the robustness of a
radio link in the presence of transient interference or due to
rapid signal fading conditions that can corrupt sections of the
message payload.
Reed-Solomon coding is also capable of improving the receiver’s
sensitivity performance by several dB, where random errors
tend to dominate under low SNR conditions and the receiver’s
packet error rate performance is limited by thermal noise.
The number of consecutive bit errors that can be 100% corrected is
{(t − 1) × 8 + 1}. Longer, random bit-error patterns, up to t bytes,
can also be corrected if the error patterns start and end at byte
boundaries.
The firmware also takes advantage of an on-chip hardware
accelerator module to enhance throughput and minimize the
latency of the Reed-Solomon processing.
PREAMBLE
Figure 75. Packet Structure with Appended Reed-Solomon ECC
WORD
SYNC
PAYLOAD
k BYTES
n BYTES
(n – k) BYTES
ECC