EVAL-ADF7023-JDB2Z Analog Devices Inc, EVAL-ADF7023-JDB2Z Datasheet - Page 57

• Manufacturer Part Number: EVAL-ADF7023-JDB2Z
• Description: BOARD EVAL ADF7023-JDB2Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB2Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

EXAMPLE LOW POWER MODES
Deep Sleep Mode 2
Deep Sleep Mode 2 is suitable for applications where the host
processor controls the low power mode timing and the lowest
possible ADF7023-J sleep current is required.
In this low power mode, the ADF7023-J is in the PHY_SLEEP
state. The BBRAM contents are not retained. This low power
mode is entered by issuing the CMD_HW_RESET command
from any radio state. To wake the part from the PHY_SLEEP
state, the CS pin should be set low. The initialization routine
after a CMD_HW_RESET command should be followed, as
detailed in the
Deep Sleep Mode 1
Deep Sleep Mode 1 is suitable for applications where the host
processor controls the low power mode timing and the ADF7023-J
configuration is retained during the PHY_SLEEP state.
In this low power mode, the ADF7023-J is in the PHY_SLEEP
state with the BBRAM contents retained. Before entering the
PHY_SLEEP state, the WUC_BBRAM_EN bit (Address 0x30D)
should be set to 1 to ensure that the BBRAM is retained. This
low power mode is entered by issuing the CMD_PHY_SLEEP
command from either the PHY_OFF or PHY_ON state. To exit
the PHY_SLEEP state, the CS pin can be set low. The CS low
initialization routine should then be followed, as detailed in the
Radio Control
WUC Mode
In this low power mode, the hardware WUC is used to wake the
ADF7023-J from the PHY_SLEEP state after a user-defined duration.
At the end of this duration, the ADF7023-J can provide an
interrupt to the host processor. While the ADF7023-J is in the
PHY_SLEEP state, the host processor can optionally be in a
deep sleep state to save power.
Before issuing the CMD_PHY_SLEEP command, the host
processor should configure the WUC and set the firmware
timer threshold to zero (NUMBER_OF_WAKEUPS_IRQ_
THRESHOLD_x = 0, Address 0x104 and Address 0x105). The
WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to
ensure that the BBRAM is retained. On issuing the CMD_PHY_
SLEEP command, the device goes to sleep for a period until the
hardware timer times out. At this point, the device wakes up,
and, if the WUC_TIMEOUT bit (Address 0x101) or the
INTERRUPT_NUM_WAKEUPS bit (Address 0x100) interrupts
are enabled, the device asserts the IRQ_GP3 pin.
The operation of this low power mode is illustrated in Figure 70.
Radio Control
section.
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WUC Mode with Firmware Timer
In this low power mode, the WUC is used to periodically wake
the ADF7023-J from the PHY_SLEEP state, and the firmware
timer is used to count the number of WUC timeouts. The
combination of the WUC and the firmware timer provides a
real-time clock (RTC) capability.
The host processor should set up the WUC and the firmware
timer before entering the PHY_SLEEP state. The WUC_
BBRAM_EN bit (Address 0x30D) should be set to 1 to ensure
that the BBRAM is retained. The WUC can be configured to
time out at some standard time interval (for example, 1 sec, 60 sec).
On issuing the CMD_PHY_SLEEP command, the device enters
the PHY_SLEEP state for a period until the hardware timer times
out. At this point, the device wakes up, increments the 16-bit
firmware timer (NUMBER_OF_WAKEUPS_x, Address 0x102 and
Address 0x103) and, if the WUC_TIMEOUT bit (Address 0x101)
is enabled, the device asserts the IRQ_GP3 pin. If the 16-bit
firmware count is less than or equal to the user set threshold
(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_x,
Address 0x104 and Address 0x105), the device returns to the
PHY_SLEEP state. With this method, the firmware count
(NUMBER_OF_WAKEUPS_x) equates to a real-time interval.
When the firmware count exceeds the user-set threshold
(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_x), the
ADF7023-J asserts the IRQ_GP3 pin, if the INTERRUPT_NUM_
WAKEUPS bit (Address 0x100) is set, and enters the PHY_OFF
state. The operation of this low power mode is illustrated in
Figure 71.
Smart Wake Mode (Carrier Sense Only)
In this low power mode, the WUC, firmware timer, and smart
wake mode are used to implement periodic RSSI measurements
on a particular channel (that is, carrier sense). To enable this
mode, the WUC and firmware timer should be configured before
entering the PHY_SLEEP state. The WUC_BBRAM_EN bit
(Address 0x30D) should be set to 1 to ensure that the BBRAM
is retained. The RSSI measurement is enabled by setting the
SWM_RSSI_QUAL bit = 1 and the SWM_EN bit = 1
(Address 0x11A). The INTERRUPT_SWM_RSSI_DET bit
(Address 0x100) should also be enabled. If the measured
RSSI value is below the user-defined threshold set in the
SWM_RSSI_THRESH register (Address 0x108), the device
returns to the PHY_SLEEP state. If the RSSI measurement is
greater than the SWM_RSSI_THRESH value, the device sets the
INTERRUPT_SWM_RSSI_DET interrupt to alert the host
processor and waits in the PHY_ON state for a host command.
The operation of this low power mode is illustrated in Figure 72.
ADF7023-J