EVAL-ADF7023-JDB2Z Analog Devices Inc, EVAL-ADF7023-JDB2Z Datasheet - Page 39

• Manufacturer Part Number: EVAL-ADF7023-JDB2Z
• Description: BOARD EVAL ADF7023-JDB2Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB2Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

If PREAMBLE_MATCH is set to 0x0C, the ADF7023-J must
receive 12 consecutive 01 pairs (three bytes) to confirm that valid
preamble has been detected. The user can select the option to
automatically lock the AFC and/or AGC once the qualified
preamble is detected. The AFC lock on preamble detection
can be enabled by setting AFC_LOCK_MODE = 3 in the
RADIO_CFG_10 register (Address 0x116). The AGC lock on
preamble detection can be enabled by setting AGC_LOCK_
MODE = 3 in the RADIO_CFG_7 register (Address 0x113).
After the preamble is detected and the end of preamble has been
reached, the communications processor searches for the sync
word. The search for the sync word lasts for a duration equal to
the sum of the number of programmed sync word bits, plus the
preamble matching tolerance (in bits) plus 16 bits. If the sync
word routine is detected during this duration, the communications
processor loads the received payload to packet RAM and computes
the CRC (if enabled). If the sync word routine is not detected
during this duration, the communications processor continues
searching for the preamble.
Preamble detection can be disabled by setting the PREAMBLE_
MATCH register to 0x00. To enable an interrupt upon preamble
detection, the user must set INTERRUPT_PREAMBLE_DETECT =
1 in the INTERRUPT_MASK_0 register (Address 0x100).
SYNC WORD
Sync word is the synchronization word used by the receiver for
byte level synchronization while also providing an optional
interrupt on detection. It is automatically added to the packet
by the communications processor in transmit mode and removed
during reception of a packet.
24 BITS ≥ SYNC_WORD_LENGTH > 16 BITS
16 BITS ≥ SYNC_WORD_LENGTH > 8 BITS
SYNC_WORD_LENGTH ≤ 8 BITS
Figure 53. Transmit Sync Word Configuration
APPEND UNUSED BITS
WITH PREAMBLE (0101..)
APPEND UNUSED BITS
WITH PREAMBLE (0101..)
APPEND UNUSED BITS
WITH PREAMBLE (0101..)
FIRST BIT SENT
MSB
MSB
MSB
SYNC_BYTE_0
SYNC_BYTE_1
SYNC_BYTE_2
Rev. 0 | Page 39 of 100
LSB
LSB
LSB
The value of the sync word is set in the SYNC_BYTE_0,
SYNC_BYTE_1, and SYNC_BYTE_2 registers (Address 0x121,
Address 0x122, and Address 0x123, respectively). The sync word is
transmitted most significant bit first starting with SYNC_BYTE_0.
The sync word matching length at the receiver is set using
SYNC_WORD_LENGTH in the SYNC_CONTROL register
(Address 0x120) and can be one bit to 24 bits long; the transmitted
sync word is a multiple of eight bits. Therefore, for nonbyte
length sync words, the transmitted sync pattern should be
appended with the preamble pattern as described in Figure 53
and Table 18.
In receive mode, the ADF7023-J can provide an interrupt on
reception of the sync word sequence programmed in the
SYNC_BYTE_0, SYNC_BYTE_1, and SYNC_BYTE_2 registers.
This feature can be used to alert the host processor that a qualified
sync word has been received. An error tolerance parameter can
also be programmed that accepts a valid match when up to three
bits of the sync word sequence are incorrect. The error tolerance
value is set using the SYNC_ERROR_TOL setting in the
SYNC_CONTROL register (Address 0x120), as described
in Table 17.
Table 17. Sync Word Detection Tolerance (SYNC_ERROR_TOL,
Bits[7:6] of Address 0x120)
Value
00
01
10
11
SYNC_BYTE_1
SYNC_BYTE_2
Description
No bit errors allowed.
One bit error allowed.
Two bit errors allowed.
Three bit errors allowed.
SYNC_BYTE_2
ADF7023-J