EVAL-ADF7023-JDB2Z Analog Devices Inc, EVAL-ADF7023-JDB2Z Datasheet - Page 15

• Manufacturer Part Number: EVAL-ADF7023-JDB2Z
• Description: BOARD EVAL ADF7023-JDB2Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB2Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

TIMING SPECIFICATIONS
V
Table 7. SPI Interface Timing
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Timing Diagrams
1
2
3
4
5
6
7
8
9
11
12
13
14
DD
= VDDBAT1 = VDDBAT2 = 3 V ± 10%, V
SCLK
MISO
MOSI
CS
SPI STATE
t
1
Limit
15
85
85
85
170
10
5
5
85
270
310
20
20
SCLK
MISO
t
CS
7
t
2
BIT 7
7
SLEEP
t
3
Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready T12 After Falling Edge of CS )
t
t
8
4
BIT 6
6
t
Unit
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
μs typ
ns max
ns max
6
t
1
t
5
WAKE UP
BIT 5
5
t
12
GND
Test Conditions/Comments
CS falling edge to MISO setup time (TRX active)
CS low to SCLK setup time
SCLK high time
SCLK low time
SCLK period
SCLK falling edge to MISO delay
MOSI to SCLK rising edge setup time
MOSI to SCLK rising edge hold time
SCLK falling edge to CS hold time
CS high time
CS low to MISO high wake-up time,
SCLK rise time
SCLK fall time
BIT 4
4
= GND = 0 V, T
t
BIT 3
13
3
Figure 2. SPI Interface Timing
Rev. 0 | Page 15 of 100
7
BIT 2
2
t
14
A
t
6
6
= T
BIT 1
1
MIN
5
to T
BIT 0
0
4
MAX
SPI READY
, unless otherwise noted.
BIT 7
26 MHz crystal with 7 pF load capacitance, T
3
7
2
1
BIT 0
0
t
9
t
X
9
X
t
11
BIT 7
ADF7023-J
7
A
= 25°C