EVAL-ADF7023-JDB2Z Analog Devices Inc, EVAL-ADF7023-JDB2Z Datasheet
EVAL-ADF7023-JDB2Z
Specifications of EVAL-ADF7023-JDB2Z
Related parts for EVAL-ADF7023-JDB2Z
EVAL-ADF7023-JDB2Z Summary of contents
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FEATURES Ultralow power, high performance transceiver Frequency bands: 902 MHz to 958 MHz Data rates supported: 1 kbps to 300 kbps 2 3.6 V power supply Single-ended and differential power amplifiers (PAs) Low IF receiver with programmable IF ...
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ADF7023-J TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 6 RF and Synthesizer Specifications.............................................. 6 Transmitter Specifications........................................................... 7 Receiver Specifications ................................................................ 9 Timing and Digital Specifications............................................ ...
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Test DAC ......................................................................................73 Transmit Test Modes ..................................................................73 Silicon Revision Readback .........................................................73 Applications Information...............................................................74 Application Circuit .....................................................................74 Host Processor Interface ............................................................74 PA/LNA Matching ......................................................................75 Command Reference ......................................................................77 REVISION HISTORY 5/11—Revision 0: Initial Version Register Maps ..................................................................................78 BBRAM Register Description ...
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ADF7023-J FUNCTIONAL BLOCK DIAGRAM LNA RFIO_1P RFIO_1N PA DIVIDER RFO2 PA PA RAMP PROFILE ADF7023-J CREGRFx CREGVCO CREGSYNTH CREGDIGx 1 GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27. GENERAL DESCRIPTION The ADF7023 very low power, ...
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RAM. In receive mode, the communications processor can detect and interrupt the host processor on reception of preamble, sync word, address, and CRC and store the received payload to packet RAM. The ADF7023-J uses an ...
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ADF7023-J SPECIFICATIONS V = VDDBAT1 = VDDBAT2 = 2 3.6 V, GND = and T = 25° AND SYNTHESIZER SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Frequency Range ...
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TRANSMITTER SPECIFICATIONS Table 2. Parameter DATA RATE 2FSK/GFSK/MSK/GMSK Data Rate Resolution 1 MODULATION ERROR RATIO (MER) 10 kbps to 49.5 kbps 49.6 kbps to 129.5 kbps 129.6 kbps to 179.1 kbps 179.2 kbps to 239.9 kbps 240 kbps to 300 ...
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ADF7023-J Parameter SPURIOUS EMISSIONS 30 MHz to 710 MHz 710 MHz to 945 MHz 945 MHz to 950 MHz 958 MHz to 960 MHz 960 MHz to 1 GHz 1 GHz to 1.215 GHz 1.215 GHz to 1.8845 GHz 5 ...
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RECEIVER SPECIFICATIONS Table 3. Parameter 2FSK/MSK INPUT SENSITIVITY, BIT ERROR RATE (BER) 1.0 kbps 10 kbps 38.4 kbps 50 kbps 100 kbps 150 kbps 200 kbps 300 kbps GFSK/GMSK INPUT SENSITIVITY, BER 50 kbps 100 kbps 100 kbps 200 kbps ...
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ADF7023-J Parameter GFSK/GMSK INPUT SENSITIVITY, PER 50 kbps 100 kbps 100 kbps 200 kbps 200 kbps LNA AND MIXER, INPUT IP3 Minimum LNA Gain Maximum LNA Gain LNA AND MIXER, INPUT IP2 Maximum LNA Gain, Maximum Mixer Gain Minimum LNA ...
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Parameter AFC Accuracy Maximum Pull-In Range 300 kHz IF Filter Bandwidth 200 kHz IF Filter Bandwidth 150 kHz IF Filter Bandwidth 100 kHz IF Filter Bandwidth PREAMBLE LENGTH AFC Off, AGC Lock on Sync Word Detection 38.4 kbps 300 kbps ...
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TIMING AND DIGITAL SPECIFICATIONS Table 4. Parameter Rx AND Tx TIMING PARAMETERS PHY_ON to PHY_RX (on CMD_PHY_RX) PHY_ON to PHY_TX (on CMD_PHY_TX) LOGIC INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current INH INL ...
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AUXILARY BLOCK SPECIFICATIONS Table 5. Parameter 32 kHz RC OSCILLATOR Frequency Frequency Accuracy Frequency Drift Temperature Coefficient Voltage Coefficient Calibration Time 32 kHz XTAL OSCILLATOR Frequency Start-Up Time WAKE UP CONTROLLER (WUC) Hardware Timer Wake-Up Period Firmware Timer Wake-Up Period ...
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ADF7023-J GENERAL SPECIFICATIONS Table 6. Parameter TEMPERATURE RANGE VOLTAGE SUPPLY V DD TRANSMIT CURRENT CONSUMPTION Single-Ended PA, 915 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm Differential PA, 915 MHz −10 dBm 0 dBm 5 dBm 10 ...
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TIMING SPECIFICATIONS V = VDDBAT1 = VDDBAT2 = 3 V ± 10 Table 7. SPI Interface Timing Parameter Limit Unit max min min ...
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ADF7023-J ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Connect the exposed paddle A of the LFCSP package to ground. Table 8. Parameter VDDBAT1, VDDBAT2 to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θ ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 9. Pin Function Descriptions Pin No. Mnemonic Description 1 CREGRF1 Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection. 2 RBIAS ...
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ADF7023-J Pin No. Mnemonic Description 21 MISO Serial Port Master In/Slave Out. 22 SCLK Serial Port Clock. 23 MOSI Serial Port Master Out/Slave In Chip Select (Active Low). A pull-up resistor of 100 kΩ processor from ...
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TYPICAL PERFORMANCE CHARACTERISTICS –2 –4 –6 –8 –10 –12 –14 –16 –18 – SETTING ...
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ADF7023 –10 –20 PA RAMP = 4 –30 PA RAMP = 5 PA RAMP = 6 –40 PA RAMP = 7 –50 – ...
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FUNDAMENTAL TONE –70 IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT –80 IM3 3/1 SLOPE FIT –90 –50 –45 –40 –35 –30 –25 LNA INPUT POWER (dBm) Figure 17. LNA/Mixer IIP3 ...
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ADF7023 25°C, 3.0V –10 –60 –50 –40 –30 –20 – BLOCKER FREQUENCY OFFSET (MHz) Figure 23. Receiver Wideband Blocking at 954 MHz, Data Rate = 50 kbps, Frequency Deviation ...
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CALIBRATED UNCALIBRATED –10 –20 –30 –40 –50 –60 –70 –80 –90 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) Figure 29. Image Attenuation with Calibrated and Uncalibrated Images, 915 MHz, IF Filter Bandwidth ...
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ADF7023 2.1dB 3 3.5dB 2 4.1dB 1 0 –107 –106 –105 –104 –103 –102 Rx INPUT POWER (dBm) Figure 35. Receiver PER Using Reed Solomon (RS) Coding; RF Frequency = 928 MHz, GFSK, ...
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INPUT POWER (dBm) Figure 41. Mean RSSI Error (via Automatic End of Packet RSSI Measurement) vs. RF Input Power vs. Data Rate; RF Frequency = 950 ...
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ADF7023-J TERMINOLOGY ADC Analog-to-digital converter AGC Automatic gain control AFC Automatic frequency control Battmon Battery monitor BBRAM Battery backup random access memory CBC Cipher block chaining CRC Cyclic redundancy check DR Data rate ECB Electronic code book ECC Error checking ...
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RADIO CONTROL The ADF7023-J has five radio states designated PHY_SLEEP, PHY_OFF, PHY_ON, PHY_TX, and PHY_RX. The host processor can transition the ADF7023-J between states by issuing single byte commands over the SPI interface. The various commands and states are illustrated ...
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ADF7023-J COLD START (BATTERY APPLIED) CMD_CONFIG_DEV CONFIGURE CMD_RAM_LOAD_INIT PROGRAM RAM CMD_RAM_LOAD_DONE CONFIG 2 PROGRAM RAM AES IR CALIBRATION REED-SOLOMON 1 TRANSMIT AND RECEIVE AUTOMATIC TURNAROUND MUST BE ENABLED BY BITS RX_TO_TX_AUTO_TURNAROUND AND TX_TO_RX_AUTO_TURNAROUND (0x11A: MODE_CONTROL). 2 AES ENCRYPTION/DECRYPTION, IMAGE REJECTION ...
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INITIALIZATION Initialization After Application of Power When power is applied to the ADF7023-J (through the VDDBAT1/VDDBAT2 pins), it registers a power-on reset (POR) event and transitions to the PHY_OFF state. The BBRAM memory is unknown, the packet RAM memory is ...
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ADF7023-J COMMANDS The commands that are supported by the radio controller are detailed in this section. They initiate transitions between radio states or perform tasks as indicated in Figure 47. The execution times for all radio state transitions are detailed ...
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If the command is issued in the PHY_TX state, the communications processor performs the following procedure: 1. Ramps down the PA. 2. Sets the external PA enable signal low (if enabled). 3. Turns off the digital transmit blocks. 4. Sets ...
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ADF7023-J CMD_AES_ENCRYPT (0xD0), CMD_AES_DECRYPT (0xD2), and CMD_AES_DECRYPT_INIT (0xD1) These commands allow AES, 128-bit block encryption and decryption of transmit and receive data using key sizes of 128 bits, 192 bits, or 256 bits. The AES commands require that the AES ...
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STATE TRANSITION AND COMMAND TIMING The execution times for all radio state transitions are detailed in Table 11 and Table 12. Note that these times are typical and can vary, depending on the BBRAM configuration. Table 11. ADF7023-J Command Execution ...
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ADF7023-J Command/Bit/ Automatic Present Mode Transition State Packet CMD_PHY_RX PHY_RX Packet TX_TO_RX_AUTO_ PHY_TX TURNAROUND Packet TX_EOF PHY_TX Packet RX_EOF PHY_RX Sport CMD_PHY_ON PHY_TX Sport CMD_PHY_ON PHY_RX Sport CMD_PHY_TX PHY_ON Sport CMD_PHY_TX PHY_RX Sport CMD_PHY_TX PHY_TX Sport PHY_RX RX_TO_TX_AUTO _TURNAROUND Sport ...
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SPORT MODE It is possible to bypass all of the packet management features of the ADF7023-J and use the sport interface for transmit and receive data. The sport interface is a high speed synchronous serial interface allowing direct interfacing to ...
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ADF7023-J Table 14. GPIO Functionality in Sport Mode GPIO_CONFIGURE GP0 GP1 0xA0 Rx data Tx data 0xA1 Rx data Tx data 0xA2 Rx data Tx data 0xA3 Rx data Tx data 0xA4 Rx data Tx data 0xA5 Rx data Tx ...
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PHY_RX CMD_PHY_RX 309µs PACKET PREAMBLE GP2 (RX CLK) GP0 (RX DATA) GP4 (GPIO_CONFIGURE = 0xA1) GP4 (GPIO_CONFIGURE = 0xA2) PREAMBLE DETECTED GP2 (RX CLK) GP0 (RX DATA) GP4 (GPIO_CONFIGURE = 0xA1) GP4 (GPIO_CONFIGURE = 0xA2) Figure 51. Sport Mode Receive, ...
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ADF7023-J PACKET MODE The on-chip communications processor can be configured for use with a wide variety of packet-based radio protocols using 2FSK/GFSK/MSK/GMSK modulation. The general packet format, when using the packet management features of the communications processor, is illustrated in ...
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If PREAMBLE_MATCH is set to 0x0C, the ADF7023-J must receive 12 consecutive 01 pairs (three bytes) to confirm that valid preamble has been detected. The user can select the option to automatically lock the AFC and/or AGC once the qualified ...
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ADF7023-J Table 18. Sync Word Programming Examples SYNC_WORD_ LENGTH Bits in Required Sync Word (Binary, SYNC_CONTROL First Bit Being First in Time) Register (0x120) 000100100011010001010110 24 111010011100101000100 21 0001001000110100 16 011100001110 12 00010010 8 011100 don’t ...
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The address data is then compared against a list of known addresses that are stored in BBRAM (Address 0x12B to Address 0x13D). Each stored address byte has an associated mask byte, thereby allowing matching of partial sections of the address ...
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ADF7023-J To convert a user-defined polynomial to the 2-byte value, the polynomial should be written in binary format. The x is assumed equal to 1 and is, therefore, discarded. The remaining 16 bits then make up CRC_POLY_0 (most significant byte) ...
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DATA WHITENING Data whitening can be employed to avoid long runs the transmitted data stream. This ensures sufficient bit transitions in the packet, which aids in receiver clock and data recovery because the encoding breaks ...
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ADF7023-J INTERRUPT GENERATION The ADF7023-J uses a highly flexible, powerful interrupt system with support for MAC level interrupts and PHY level interrupts. To enable an interrupt source, the corresponding mask bit must be set. When an enabled interrupt occurs, the ...
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Register Bit Name INTERRUPT_MASK_1, 7 BATTERY_ALARM Address 0x101 6 CMD_READY 5 Reserved 4 WUC_TIMEOUT 3 Reserved 2 Reserved 1 SPI_READY 0 CMD_FINISHED Table 24. Structure of the Interrupt Source Registers Register Bit Name INTERRUPT_SOURCE_0, 7 INTERRUPT_NUM_WAKEUPS Address: 0x336 6 INTERRUPT_SWM_RSSI_DET ...
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ADF7023-J INTERRUPTS IN SPORT MODE In sport mode, the interrupts from INTERRUPT_SOURCE_1 are all available. However, only INTERRUPT_PREAMBLE_DETECT and INTERRUPT_SYNC_DETECT are available from INTERRUPT_SOURCE_0. A second interrupt pin is provided on GP4, which gives a dedicated sport mode interrupt on ...
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ADF7023-J MEMORY MAP MISO MOSI SCLK COMMS PROCESSOR CLOCK This section describes the various memory locations used by the ADF7023-J. The radio control, packet management, and smart wake mode capabilities of the part are realized using an integrated RISC processor, ...
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ADF7023-J PACKET RAM The packet RAM consists of 256 bytes of memory space. The first 16 bytes of this memory space are allocated for use by the on-chip processor. The remaining 240 bytes of this memory space are allocated for ...
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SPI INTERFACE GENERAL CHARACTERISTICS The ADF7023-J is equipped with a 4-wire SPI interface, using the SCLK, MISO, MOSI, and CS pins. The ADF7023-J always acts as a slave to the host processor. Figure 59 connection diagram between the processor and ...
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ADF7023-J Table 26. FW_STATE Description Value State 0x0F Initializing 0x00 Busy, performing a state transition 0x11 PHY_OFF 0x12 PHY_ON 0x13 PHY_RX 0x14 PHY_TX 0x06 PHY_SLEEP 0x05 Performing CMD_GET_RSSI 0x07 Performing CMD_IR_CAL 0x08 Performing CMD_AES_DECRYPT_INIT 0x09 Performing CMD_AES_DECRYPT 0x0A Performing CMD_AES_ENCRYPT ...
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MEMORY ACCESS Memory locations are accessed by invoking the relevant SPI command. An 11-bit address is used to identify registers or locations in the memory space. The most significant three bits of the address are incorporated into the SPI command ...
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ADF7023-J Random Address Write MCR, BBRAM, and packet RAM memory locations can be written nonsequential manner using the SPI_MEMR_WR command. The SPI_MEMR_WR command code is 00001xxxb, where xxxb represent Bits[10:8] of the 11-bit address. The lower eight ...
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CS SPI_MEM_RD MOSI IGNORE MISO CS SPI_MEMR_RD ADDRESS 1 MOSI MISO IGNORE STATUS Figure 68. Memory (MCR, BBRAM, or Packet RAM) Random Address Read ADDRESS SPI_NOP SPI_NOP DATA FROM STATUS STATUS ADDRESS Figure 67. Memory (MCR, BBRAM, or Packet RAM) ...
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ADF7023-J LOW POWER MODES The ADF7023-J can be configured to operate in a broad range of energy sensitive applications where battery lifetime is critical. This includes support for applications where the ADF7023-J is required to operate in a fully autonomous ...
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Low Power Memory Mode Address Register Name SWM 0x108 SWM_RSSI_THRESH SWM 0x107 PARMTIME_DIVIDER SWM 0x106 RX_DWELL_TIME SWM 0x100 INTERRUPT_MASK_0 necessary to write to the 0x30C and 0x30D registers in the following order: WUC_CONFIG_HIGH (Address 0x30C), directly followed ...
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ADF7023-J MEASURE RSSI NO RSSI > THRESHOLD (SWM_RSSI_THRESH) YES RSSI INT ENABLED? (INTERRUPT_ SWM_RSSI_DET) NO RX_DWELL_TIME EXCEEDED ADF7023-J PHY_SLEEP NO BBRAM RETAINED? YES NO WUC CONFIGURED? YES INCREMENT NUMBER_OF_WAKEUPS NUMBER_OF_WAKEUPS YES > THRESHOLD? NO SWM ENABLED? NO (SWM_EN = 1) ...
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EXAMPLE LOW POWER MODES Deep Sleep Mode 2 Deep Sleep Mode 2 is suitable for applications where the host processor controls the low power mode timing and the lowest possible ADF7023-J sleep current is required. In this low power mode, ...
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ADF7023-J Smart Wake Mode In this low power mode, the WUC, firmware timer, and smart wake mode are employed to periodically listen for packets. To enable this mode, the WUC and firmware timer should be configured and smart wake mode ...
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LOW POWER MODE TIMING DIAGRAMS ADF7023-J OPERATION INTERRUPT WUC_TIMEOUT (IF ENABLED) INTERRUPT INTERRUPT_NUM_WAKEUPS (IF ENABLED AND NUMBER_OF_WAKEUPS_IRQ_THRESHOLD = 0) HOST: CMD_PHY_SLEEP HOST: START WUC PHY_OFF OR ADF7023-J PHY_ON OPERATION INTERRUPT_ NUM_WAKEUPS Figure 71. Low Power Mode Timing When Using the ...
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ADF7023-J WUC SETUP Circuit Description The ADF7023-J features a low power wake-up controller comprising a 16-bit wake-up timer with a 3-bit programmable prescaler, as illustrated in Figure 74. The prescaler clock source can be configured to use either the 32.76 ...
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WUC Setting WUC_CONFIG_LOW[7] WUC_CONFIG_LOW[6] WUC_CONFIG_LOW[5] WUC_CONFIG_LOW[4] WUC_CONFIG_LOW [3] WUC_CONFIG_LOW[2:1] WUC_CONFIG_LOW[0] FIRMWARE TIMER SETUP The ADF7023-J wakes up from the PHY_SLEEP state at the rate set by the WUC. A firmware timer, implemented by the on-chip processor, can be used to ...
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ADF7023-J DOWNLOADABLE FIRMWARE MODULES The program RAM memory of the ADF7023-J can be used to store firmware modules for the communications processor that provide the ADF7023-J with extra functionality. The binary code for these firmware modules and details on their ...
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PLAIN TEXT 128 BITS KEY AES ENCRYPT 128 BITS CIPHER TEXT PLAIN TEXT 128 BITS INITIAL VECTOR + KEY KEY AES ENCRYPT 128 BITS CIPHER TEXT ECB MODE 128 BITS 128 BITS KEY KEY AES AES ENCRYPT ENCRYPT 128 BITS ...
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ADF7023-J RADIO BLOCKS FREQUENCY SYNTHESIZER A fully integrated RF frequency synthesizer is used to generate both the transmit signal and the receiver’s local oscillator (LO) signal. The architecture of the frequency synthesizer is shown in Figure 78. The receiver uses ...
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Synthesizer Settling After the VCO calibration μs delay is allowed for synthesizer settling. This delay is fixed at 56 μs by default and ensures that the synthesizer has fully settled when using any of the default synthesizer bandwidths. ...
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ADF7023-J RF OUTPUT STAGE Power Amplifier (PA) The ADF7023-J PA can be configured for single-ended or differential output operation using the PA_SINGLE_DIFF_SEL bit in the RADIO_CFG_8 register (Address 0x114). The PA level is set by the PA_LEVEL bit in the ...
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The AGC remains at each gain stage for a time defined by the AGC_CLK_DIVIDE register (Address 0x32F). The default value of AGC_CLK_DIVIDE = 0x28 gives an AGC delay of 25 μs. When the RSSI is above AGC_HIGH_THRESHOLD (Address 0x35F), the ...
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ADF7023-J Table 36. Summary of RSSI Measurement Methods RSSI Method RSSI Type Modulation 1 Automatic end of 2FSK/GFSK/ packet RSSI MSK/GMSK 2 CMD_GET_RSSI 2FSK/GFSK/ command from MSK/GMSK PHY_ON 3 RSSI via ADC and 2FSK/GFSK/ AGC readback, FSK MSK/GMSK Available in ...
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IF FILTER MIXER LNA RFIO_1P RFIO_1N IF IFBW[1:0] (ADDRESS RADIO_CFG_9[7:6]) AFC SYSTEM RF RANGE SYNTHESIZER (LO) MAX_AFC_RANGE[7:0] 2FSK/GFSK/MSK/GMSK DEMODULATION A correlator demodulator is used for 2FSK, GFSK, MSK, and GMSK demodulation. The quadrature outputs of the IF filter are first ...
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ADF7023-J Step 3: Calculate the DISCRIM_PHASE Setting The phase setting of the discriminator is calculated based on the Discriminator Coefficient K, as described in Table 37. The phase is set using the DISCRIM_PHASE[1:0] value in the RADIO_CFG_6 register (Address 0x112). ...
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CLOCK RECOVERY An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock in all modulation modes. The maximum symbol rate tolerance of the CDR PLL is determined by the ...
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ADF7023-J Table 41. Summary of Recommended AGC, AFC, Preamble Length, and Sync Word Error Tolerance for 2FSK/GFSK/MSK/GMSK AFC Data Frequency IF Pull-In Rate Deviation BW Range (kbps) (kHz) (kHz) (kHz) 300 75 300 ±150 200 50 200 ±100 150 37.5 ...
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PERIPHERAL FEATURES ANALOG-TO-DIGITAL CONVERTER The ADF7023-J supports an integrated SAR ADC for digitization of analog signals that include the analog temperature sensor, the analog RSSI level, and an external analog input signal (Pin 30). The conversion time is typically 1 ...
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ADF7023-J APPLICATIONS INFORMATION APPLICATION CIRCUIT A typical application circuit for the ADF7023-J is shown in Figure 83. All external components required for operation of the device, excluding supply decoupling capacitors, are shown. This example circuit uses a combined single-ended PA ...
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PA/LNA MATCHING The ADF7023-J has a differential LNA and both a single-ended PA and differential PA. This flexibility allows numerous possibilities in interfacing the ADF7023-J to the antenna. Combined Single-Ended PA and LNA Match The combined single-ended PA and LNA ...
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ADF7023-J TX (DIFFERENTIAL PA) AND RX TX (SINGLE- ENDED PA) Transmit Antenna Diversity Transmit antenna diversity is possible using the differential PA and single-ended PA. The required matching network is shown in Figure 87. Support for External PA and LNA ...
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COMMAND REFERENCE Table 45. Radio Controller Commands Command Code Description CMD_SYNC 0xA2 Synchronizes the communications processor to the host processor after reset. CMD_PHY_OFF 0xB0 Performs a transition of the device into the PHY_OFF state. CMD_PHY_ON 0xB1 Performs a transition of ...
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ADF7023-J REGISTER MAPS Table 47. Battery Backup Memory (BBRAM) Address (Hex) Register 0x100 INTERRUPT_MASK_0 0x101 INTERRUPT_MASK_1 0x102 NUMBER_OF_WAKEUPS_0 0x103 NUMBER_OF_WAKEUPS_1 0x104 NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0 0x105 NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1 0x106 RX_DWELL_TIME 0x107 PARMTIME_DIVIDER 0x108 SWM_RSSI_THRESH 0x109 CHANNEL_FREQ_0 0x10A CHANNEL_FREQ_1 0x10B CHANNEL_FREQ_2 0x10C RADIO_CFG_0 0x10D RADIO_CFG_1 ...
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Table 48. Modem Configuration Memory (MCR) Address (Hex) Register 0x307 PA_LEVEL_MCR 0x30C WUC_CONFIG_HIGH 0x30D WUC_CONFIG_LOW 0x30E WUC_VALUE_HIGH 0x30F WUC_VALUE_LOW 0x310 WUC_FLAG_RESET 0x311 WUC_STATUS 0x312 RSSI_READBACK 0x315 MAX_AFC_RANGE 0x319 IMAGE_REJECT_CAL_CONFIG 0x322 CHIP_SHUTDOWN 0x324 POWERDOWN_RX 0x325 POWERDOWN_AUX 0x327 ADC_READBACK_HIGH 0x328 ADC_READBACK_LOW 0x32D ...
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ADF7023-J Table 49. Packet RAM Memory Address Register 0x000 VAR_COMMAND 1 0x001 Product code, most significant byte = 0x70 1 0x002 Product code, least significant byte = 0x23 1 0x003 Silicon revision code, most significant byte 1 0x004 Silicon revision ...
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Table 52. 0x102: NUMBER_OF_WAKEUPS_0 Bit Name [7:0] NUMBER_OF_WAKEUPS[7:0] Table 53. 0x103: NUMBER_OF_WAKEUPS_1 Bit Name [7:0] NUMBER_OF_WAKEUPS[15:8] Table 54. 0x104: NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_0 Bit Name [7:0] NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[7:0] Table 55. 0x105: NUMBER_OF_WAKEUPS_IRQ_THRESHOLD_1 Bit Name [7:0] NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:8] Table 56. 0x106: RX_DWELL_TIME Bit Name [7:0] RX_DWELL_TIME ...
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ADF7023-J Table 60. 0x10A: CHANNEL_FREQ_1 Bit Name [7:0] CHANNEL_FREQ[15:8] Table 61. 0x10B: CHANNEL_FREQ_2 Bit Name [7:0] CHANNEL_FREQ[23:16] Table 62. 0x10C: RADIO_CFG_0 Bit Name R/W [7:0] DATA_RATE[7:0] R/W Table 63. 0x10D: RADIO_CFG_1 Bit Name [7:4] FREQ_DEVIATION[11:8] [3:0] DATA_RATE[11:8] Table 64. 0x10E: ...
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Table 69. 0x113: RADIO_CFG_7 Bit Name [7:6] AGC_LOCK_MODE [5:4] SYNTH_LUT_CONTROL [3:0] SYNTH_LUT_CONFIG_1 Table 70. 0x114: RADIO_CFG_8 Bit Name R/W Description [7] PA_SINGLE_DIFF_SEL R/W PA_SINGLE_DIFF_SEL 0 1 [6:3] PA_LEVEL R/W Sets the PA output power. A value of zero sets the ...
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ADF7023-J Bit Name R/W Description [2:0] PA_RAMP R/W Sets the PA ramp rate. The PA ramps at the programmed rate until it reaches the level indicated by the PA_LEVEL_MCR (Address 0x307) setting. The ramp rate is dependent on the programmed ...
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Table 73. 0x117: RADIO_CFG_11 Bit Name [7:4] AFC_KP [3:0] AFC_KI Table 74. 0x118: IMAGE_REJECT_CAL_PHASE Bit Name [7] Reserved [6:0] IMAGE_REJECT_CAL_PHASE Table 75. 0x119: IMAGE_REJECT_CAL_AMPLITUDE Bit Name [7] Reserved [6:0] IMAGE_REJECT_CAL_AMPLITUDE Table 76. 0x11A: MODE_CONTROL Bit Name [7] SWM_EN [6] BB_CAL ...
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ADF7023-J Table 77. 0x11B: PREAMBLE_MATCH Bit Name [7] EXT_PA_LNA_CONFIG [6:4] Reserved [3:0] PREAMBLE_MATCH Table 78. 0x11C: SYMBOL_MODE Bit Name [7] Reserved [6] MANCHESTER_ENC [5] PROG_CRC_EN [4] EIGHT_TEN_ENC [3] DATA_WHITENING [2:0] SYMBOL_LENGTH Table 79. 0x11D: PREAMBLE_LEN Bit Name [7:0] PREAMBLE_LEN Table ...
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Table 82. 0x120: SYNC_CONTROL Bit Name [7:6] SYNC_ERROR_TOL [5] Reserved [4:0] SYNC_WORD_LENGTH Table 83. 0x121: SYNC_BYTE_0 Bit Name [7:0] SYNC_BYTE[7:0] Table 84. 0x122: SYNC_BYTE_1 Bit Name [7:0] SYNC_BYTE[15:8] Table 85. 0x123: SYNC_BYTE_2 Bit Name [7:0] SYNC_BYTE[23:16] Table 86. 0x124: TX_BASE_ADR ...
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ADF7023-J Table 88. 0x126: PACKET_LENGTH_CONTROL Bit Name [7] DATA_BYTE [6] PACKET_LEN [5] CRC_EN [4:3] DATA_MODE [2:0] LENGTH_OFFSET Table 89. 0x127: PACKET_LENGTH_MAX Bit Name [7:0] PACKET_LENGTH_MAX R/W Description R/W Over-the-air arrangement of each transmitted packet RAM byte. A byte is transmitted ...
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Table 90. 0x128: STATIC_REG_FIX Bit Name [7:0] STATIC_REG_FIX Table 91. 0x129: ADDRESS_MATCH_OFFSET Bit Name [7:0] ADDRESS_MATCH_OFFSET Table 92. 0x12A: ADDRESS_LENGTH Bit Name [7:0] ADDRESS_LENGTH Table 93. 0x12B to 0x13D: Address Matching Address Bit 0x12B [7:0] 0x12C [7:0] 0x12D [7:0] 0x12E ...
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ADF7023-J MCR REGISTER DESCRIPTION The MCR register settings are not retained when the device enters the PHY_SLEEP state. Table 96. 0x307: PA_LEVEL_MCR Bit Name [5:0] PA_LEVEL_MCR Table 97. 0x30C: WUC_CONFIG_HIGH Bit Name [7] Reserved [6] WUC_BGAP [5] WUC_LDO_SYNTH [4] WUC_LDO_DIG ...
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Register WUC_VALUE_LOW should never be written to without updating register WUC_VALUE_HIGH first. Table 100. 0x30F: WUC_VALUE_LOW Bit Name [7:0] WUC_TIMER_VALUE[7:0] Table 101. 0x310: WUC_FLAG_RESET Bit Name [1] WUC_RCOSC_CAL_EN [0] WUC_FLAG_RESET Table 102. 0x311: WUC_STATUS Bit Name [7] Reserved [6] WUC_RCOSC_CAL_ERROR ...
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ADF7023-J Table 105. 0x319: IMAGE_REJECT_CAL_CONFIG Bit Name [7:6] Reserved [5] IMAGE_REJECT_CAL_OVWRT_EN [4:3] IMAGE_REJECT_FREQUENCY [2:0] IMAGE_REJECT_POWER Table 106. 0x322: CHIP_SHUTDOWN Bit Name [7:1] Reserved [0] CHIP_SHTDN_REQ Table 107. 0x324: POWERDOWN_RX Bit Name [7:5] Reserved [4] ADC_PD_N [3] RSSI_PD_N [2] RXBBFILT_PD_N [1] ...
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Table 110. 0x328: ADC_READBACK_LOW Bit Name [7:6] ADC_READBACK[1:0] [5:0] Reserved Table 111. 0x32D: BATTERY_MONITOR_THRESHOLD_VOLTAGE Bit Name [7:5] Reserved [4:0] BATTMON_VOLTAGE Table 112. 0x32E: EXT_UC_CLK_DIVIDE Bit Name [7:4] Reserved [3:0] EXT_UC_CLK_DIVIDE Table 113. 0x32F: AGC_CLK_DIVIDE Bit Name [7:0] AGC_CLOCK_DIVIDE Table 114. ...
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ADF7023-J Table 116. 0x338: CALIBRATION_CONTROL Bit Name [7:2] Reserved [1] SYNTH_CAL_EN [0] RXBB_CAL_EN Table 117. 0x339: CALIBRATION_STATUS Bit Name [7:3] Reserved [2] PA_RAMP_FINISHED [1] SYNTH_CAL_READY [0] RXBB_CAL_READY Table 118. 0x345: RXBB_CAL_CALWRD_READBACK Bit Name [5:0] RXBB_CAL_CALWRD Table 119. 0x346: RXBB_CAL_CALWRD_OVERWRITE Bit ...
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Table 122. 0x35C: AGC_CONFIG Bit Name [7:6] LNA_GAIN_CHANGE_ORDER [5:4] MIXER_GAIN_CHANGE_ORDER [3:2] FILTER_GAIN_CHANGE_ORDER [1] ALLOW_EXTRA_LO_LNA_GAIN [0] DISALLOW_MAX_GAIN Table 123. 0x35D: AGC_MODE Bit Name [7] Reserved [6:5] AGC_OPERATION_MCR [4:3] LNA_GAIN [2] MIXER_GAIN [1:0] FILTER_GAIN Table 124. 0x35E: AGC_LOW_THRESHOLD Bit Name [7:0] AGC_LOW_THRESHOLD ...
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ADF7023-J Table 128. 0x3CB: VCO_BAND_OVRW_VAL Bit Name [7:0] VCO_BAND_OVRW_VAL Table 129. 0x3CC: VCO_AMPL_OVRW_VAL Bit Name [7:0] VCO_AMPL_OVRW_VAL Table 130. 0x3CD: VCO_OVRW_EN Bit Name [7:6] Reserved [5:2] VCO_Q_AMP_REF [1] VCO_AMPL_OVRW_EN [0] VCO_BAND_OVRW_EN Table 131. 0x3D0: VCO_CAL_CFG Bit Name [7:4] Reserved [3:0] ...
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Table 137. 0x3FA: GPIO_CONFIGURE Bit Name [7:0] GPIO_CONFIGURE Table 138. 0x3FD: TEST_DAC_GAIN Bit Name [7:4] Reserved [3:0] TEST_DAC_GAIN PACKET RAM REGISTER DESCRIPTION Table 139. 0x00D: VAR_TX_MODE VAR_TX_MODE 255 R/W Reset Description R/W 0 0x00: ...
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... PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADF7023-JBCPZ −40°C to +85°C ADF7023-JBCPZ-RL −40°C to +85°C EVAL-ADF7XXXMB3Z EVAL-ADF7023-JDB1Z EVAL-ADF7023-JDB2Z RoHS Compliant Part. 5.10 0.30 5.00 SQ 0.25 4.90 0. 0.50 BSC 17 16 0.50 TOP VIEW BOTTOM VIEW ...
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NOTES Rev Page 99 of 100 ADF7023-J ...
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ADF7023-J NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09555-0-5/11(0) Rev Page 100 of 100 ...