MT18HTS25672RHZ-80EH1 Micron Technology Inc, MT18HTS25672RHZ-80EH1 Datasheet - Page 21

• Manufacturer Part Number: MT18HTS25672RHZ-80EH1
• Description: MODULE DDR2 SDRAM 2GB 200SORDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT18HTS25672RHZ-80EH1

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 800MT/s
• Features: -
• Package / Case: 200-SORDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Temperature Trip Point Registers
Table 22: Alarm Temperature Lower Boundary Register (Address: 0x02)
Table 23: Alarm Temperature Lower Boundary Register (Address: 0x03)
Critical Temperature Register
Table 24: Critical Temperature Register (Address: 0x04)
Temperature Register
PDF: 09005aef83f287c1
hts18c256x72rhz.pdf - Rev. A 3/10 EN
15
15
15
0
0
0
14
14
14
0
0
0
13
13
13
0
0
0
MSB
MSB
MSB
12
12
12
The upper and lower temperature boundary registers are used to set the maximum and
minimum values of the alarm window. LSB for these registers is 0.25°C. All RFU bits in
the register will always report zero.
The critical temperature register is used to set the maximum temperature above the
alarm window. The LSB for this register is 0.25°C. All RFU bits in the register will always
report zero.
The temperature register is a read-only register that provides the current temperature
detected by the temperature sensor. The LSB for this register is 0.0625°C with a resolu-
tion of 0.0625°C. The most significant bit (MSB) is 128°C in the readout section of this
register.
The upper three bits of the register are used to monitor the trip points that are set in the
previous three registers.
11
11
11
Temperature Sensor with Serial Presence-Detect EEPROM
10
10
10
Alarm window upper boundary temperature
Alarm window lower boundary temperature
2GB (x72, ECC, DR) 200-Pin DDR2 SDRAM SORDIMM
9
9
9
Critical temperature trip point
8
8
8
Bit
Bit
Bit
21
7
7
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
6
6
6
5
5
5
4
4
4
© 2010 Micron Technology, Inc. All rights reserved.
3
3
3
LSB
LSB
LSB
2
2
2
RFU
RFU
RFU
1
1
1
RFU
RFU
RFU
0
0
0